mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 132

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

7-4
Bit
Bit
3
2
1
0
2
1
0
VADDR
RxCLK
TxCLK
HLOOP
VCRC
ARTST
Name
Name
RSV
FTST
Table 152 - HDLC Test Control Register
Table 153 - HDLC Test Status Register
(Page B & C, Address 1BH)
(Page B & C, Address 1CH)
These bits are reserved.
Receive Clock. This bit represents the receiver clock generated
after the RXEN control bit, but before zero deletion is considered.
Transmit Clock. This bit represents the transmit clock generated
after the TXEN control bit, but before zero insertion is considered.
Valid CRC. This is the CRC recognition status bit for the receiver.
Data is clocked into the register and then this bit is monitored to see
if comparison was successful (bit will be high).
Valid Address. This is the address recognition status bit for the
receiver. Data is clocked into the Address Recognition Register and
then this bit is monitored to see if comparison was successful (bit
will be high).
FIFO Test. This bit allows the writing to the RX FIFO and reading
of the TX FIFO through the microprocessor to allow more efficient
testing of the FIFO status/interrupt functionality. This is done by
making a TX FIFO write become a RX FIFO write and a RX FIFO
read become a TX FIFO read. In addition, EOP/FA and RQ8/RQ9
are re-defined to be accessible (i.e. RX write causes EOP/FA to
go to RX fifo input; TX read looks at output of TX fifo through
RQ8/RQ9 bits).
Address Recognition Test. This bit allows direct access to the
Address Recognition Registers in the receiver through the serial
interface to allow more efficient testing. After address testing is
enabled, serial data is clocked in until the data aligns with the
internal address comparison (16 RXc clock cycles) and then clock
is stopped.
TR Loopback. When high, transmit to receive HDLC loopback will
be activated. The packetized transmit data will be looped back to
the receive input. RXEN and TXEN bits must also be enabled.
Zarlink Semiconductor Inc.
MT9074
132
Functional Description
Functional Description
Data Sheet