mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 129

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

7-0
Bit
Bit
7
6
5
4
3
2
1
0
FA:TxUNDERIM
RxEOPIM
RxOVFIM
TxEOPIM
RxFRST
RxFEIM
RxFFIM
TxFRST
TxFLIM
TxCRCI
INTSEL
CYCLE
SEVEN
Name
Name
GaIM
RSV
RSV
Table 147 - HDLC Interrupt Mask Register
Table 146 - HDLC Control Register 2
Interrupt Selection. When high, this bit will cause bit 2 of the Interrupt
Register to reflect a TX FIFO underrun (TXunder). When low, this interrupt
will reflect a frame abort (FA).
Cycle. When high, this bit will cause the transmit byte count to cycle through
the value loaded into the Transmit Byte Count Register.
Transmit CRC Inhibited. When high, this bit will inhibit transmission of the
CRC. That is, the transmitter will not insert the computed CRC onto the bit
stream after seeing the EOP tag byte. This is used in V.120 terminal
adaptation for synchronous protocol sensitive UI frames.
Seven Bit Address Recognition. When high, this bit will enable seven bits
of address recognition in the first address byte. The received address byte
must have bit 0 equal to 1 which indicates a single address byte is being
received.
Reserved, must be zero for normal operation.
Reserved, must be zero for normal operation.
RX FIFO Reset. When high, the RX FIFO will be reset. This causes the
receiver to be disabled until the next reception of a flag. The status register
will identify the FIFO as being empty. However, the actual bit values in the
RX FIFO will not be reset.
TX FIFO Reset. When high, the TX FIFO will be reset. The Status Register
will identify the FIFO as being empty. This bit will be reset when data is
written to the TX FIFO. However, the actual bit values of data in the TX
FIFO will not be reset. It is cleared by the next write to the TX FIFO.
This register is used with the Interrupt Register to mask out the interrupts
that are not required by the microprocessor. Interrupts that are masked out
will not drive the pin IRQ low; however, they will set the appropriate bit in the
Interrupt Register. An interrupt is disabled when the microprocessor writes a
0 to a bit in this register.
This register is cleared on power reset.
(Page B & C, Address 15H)
(Page B & C, Address 16H)
Zarlink Semiconductor Inc.
MT9074
129
Functional Description
Functional Description
Data Sheet