mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 35

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

MT9074
Data Sheet
Data Link Operation
Data Link Operation in E1 Mode
In E1 mode MT9074 has a user defined 4, 8, 12, 16 or 20 kbit/s data link for transport of maintenance and
performance monitoring information across the PCM30 link. This channel functions using the S
bits (S
~S
) of
a
a4
a8
the PCM30 timeslot zero non-frame alignment signal (NFAS). Since the NFAS is transmitted every other frame - a
periodicity of 250 microseconds - the aggregate bit rate is a multiple of 4 kb/s. As there are five S
bits
a
independently available for this data link, the bit rate will be 4, 8, 12, 16 or 20 kb/s, depending on the bits selected
for the Data Link (DL).
The S
bits used for the DL are selected by setting the appropriate bits, S
~S
, to one in the Data Link Select
a
a4
a8
Word (page 01H, address 17H, bits 4-0). Access to the DL is provided by pins TxDLCLK, TxDL, RxDLCLK and
RxDL, which allow easy interfacing to an external controller.
Data to be transmit onto the line in the S
bit position is clocked in from the TxDL pad (pin 65 in PLCC, pin 62 in
a
MQFP) with the clock TxDLCLK (pin 64 in PLCC, pin 61 in MQFP). Although the aggregate clock rate equals the bit
rate, it has a nominal pulse width of 244 ns, and it clocks in the TxDL as if it were a 2.048 Mb/s data stream. The
clock can only be active during bit times 4 to 0 of the STBUS frame. The TxDL input signal is clocked into the
MT9074 by the rising edge of TxDLCLK. If bits are selected to be a part of the DL, all other programmed functions
for those S
bit positions are overridden.
a
The RxDLCLK signal (pin 39 in PLCC, pin 20 in MQFP) is derived from the receive extracted clock and is aligned
with the receive data link output RxDL. The HDB3 decoded receive data, at 2.048 Mbit/s, is clocked out of the
device on pin RxDL (pin 40 in PLCC, pin 21 in MQFP). In order to facilitate the attachment of this data stream to a
Data Link controller, the clock signal RxDLCLK consists of positive pulses, of nominal width of 244 ns, during the Sa
bit cell times that are selected for the data link. Again, this selection is made by programming address 17H of
master control page 01H. No DL data will be lost or repeated when a receive frame slip occurs. See the AC
Electrical Characteristics for timing requirements.
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Zarlink Semiconductor Inc.