mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 43

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

MT9074
Data Sheet
Slip Buffers
Slip Buffer in T1 Mode
In T1 mode, MT9074 contains two sets of slip buffers, one on the transmit side, and one on the receive side. Both
sides may perform a controlled slip. The mechanisms that govern the slip function are a function of backplane
timing and the mapping between the ST-BUS channels and the DS1 channels. The slip mechanisms are different
for the transmit and receive slip buffers. The extracted 1.544 Mhz clock (E1.5o) and the internally generated
transmit 1.544 Mhz clock are distinct. Slips on the transmit side are independent from slips on the receive side.
The transmit slip buffer has data written to it from the near end 2.048 Mb/s stream. The data is clocked out of the
buffer using signals derived from the transmit 1.544 Mhz clock. The transmit 1.544 Mhz clock is always phase
locked to the DSTi 2.048 Mb/s stream. If the system 4.096 Mhz clock (C4b) is internally generated (pin BS/LS low),
then it is hard locked to the 1.544 Mhz clock. No phase drift or wander can exist between the two signals - therefore
no slips will occur. The delay through the transmit elastic buffer is then fixed, and is a functions of the relative
mapping between the DSTi channels and the DS1 timeslots. These delays vary with the position of the channel in
the frame. For example, DS1 timeslot 1 sits in the elastic buffer for approximately 1 usec and DS1 timeslot 24 sits in
the elastic buffer for approximately 32 usec.
If the system 4.096 Mhz clock (C4b) is externally generated (pin BS/LS high), the transmit 1.544 Mhz clock is phase
locked to it, but the PLL is designed to filter jitter present in the C4b clock. As a result phase drift will result between
the two signals. The delay through the transmit elastic buffer will vary in accordance with the input clock drift, as
well as being a function of the relative mapping between the DSTi channels and the DS1 timeslots. If the read
pointers approach the write pointers (to within approximately 1 usec) or the delay through the transmit buffer
exceeds 218 usecs a controlled slip will occur. The contents of a single frame of DS1 data will be skipped or
repeated; a maskable interrupt (masked by setting bit 1 - TxSLPI high in Interrupt Mask Word Zero - page 1H,
address 1bH) will be generated, and the status bit TSLIP (page 3H, address 17H) of MSB Transmit Slip Buffer
register will toggle. The direction of the slip is indicated by bit 6 of the same register (TSLPD). The relative phase
delay between the system frame boundary and the transmit elastic frame read boundary is measured every frame
and reported in the Transmit Slip Buffer Delay register- (page 3H, address 17H). In addition the relative offset
between these frame boundaries may be programmed by writing to this register. Every write to Transmit Elastic
Buffer Set Delay Word resets the transmit elastic frame count bit TxSBMSB (address 17H, page 3H). After a write
the delay through the slip buffer is less than 1 frame in duration. Each write operation will result in a disturbance of
the transmit DS1 frame boundary, causing the far end to go out of sync. Writing BC (hex) into the TxSBDLY register
maximizes the wander tolerance before a controlled slip occurs. Under normal operation no slips should occur in
the transmit path. Slips will only occur if the input C4b clock has excess wander, or the Transmit Elastic Buffer Set
Delay Word register is initialized too close to the slip pointers after system initialization.
The two frame receive elastic buffer is attached between the 1.544 Mbit/s DS1 receive side and the 2.048 Mbit/s
ST-BUS side of the MT9074. Besides performing rate conversion, this elastic buffer is configured as a slip buffer
which absorbs wander and low frequency jitter in multi-trunk applications. The received DS1 data is clocked into the
slip buffer with the E1.5o clock and is clocked out of the slip buffer with the system C4b clock. The E1.5o extracted
clock is generated from, and is therefore phase-locked with, the receive DS1 data. In the case of Internal mode (pin
BS/LS set low) operation, the E1.5o clock may be phase-locked to the C4b clock by an internal phase locked loop
(PLL). Therefore, in a single trunk system the receive data is in phase with the E1.5o clock, the C4b clock is phase
locked to the E1.5o clock, and the read and write positions of the slip buffer track each other.
In a multi-trunk slave or loop-timed system (i.e., PABX application) a single trunk will be chosen as a network
synchronizer, which will function as described in the previous paragraph. The remaining trunks will use the system
timing derived from the synchronizer to clock data out of their slip buffers. Even though the DS1 signals from the
network are synchronous to each other, due to multiplexing, transmission impairments and route diversity, these
signals may jitter or wander with respect to the synchronizing trunk signal. Therefore, the C1.50 clocks of
non-synchronized trunks may wander with respect to the C1.50 clock of the synchronizer and the system bus.
Network standards state that, within limits, trunk interfaces must be able to receive error-free data in the presence
of jitter and wander (refer to network requirements for jitter and wander tolerance). The MT9074 will allow 92 usec
(140 UI, DS1 unit intervals) of wander and low frequency jitter before a frame slip will occur.
43
Zarlink Semiconductor Inc.