mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 62

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

4 - 3
Bit
7
6
5
2
1
0
Bit
7
6
5
4
MFReFR
SLC96
RS1- 0
Name
ReFR
CXC
ESF
FSI
TXSECY
Extended Super Frame. Setting this bit enables transmission and reception of the 24 frame
superframe DS1 protocol.
SLC96 Mode Select. Setting this bit enables input and output of the Fs bit pattern on the
TxDL and RxDL pins. Frame synchronization is the same as in the case of D4 operation.
The transmitter will insert A and B bits every 6 frames after synchronizing to the Fs pattern
clocked into Txdl. Receive Fs bits are not monitored for the Framing Bit Error Counter.
Cross Check. Setting this bit in ESF mode enables a cross check of the CRC-6 remainder
before the frame synchronizer pulls into sync. This process adds at least 6 milliseconds to
the frame synchronization time. Setting this bit in D4 (not ESF) mode enables a check of the
Fs bits in addition to the Ft bits during frame synchronization
Reframe Select 1 - 0. These bits set the criteria for an automatic reframe in the event of
framing bits errors. The combinations available are:
RS1 - 0, RS0 - 0 = sliding window of 2 errors out of 4.
RS1 - 0, RS0 - 1 = sliding window of 2 errors out of 5.
RS1 - 1, RS0 - 0 = sliding window of 2 errors out of 6.
RS1 - 1, RS0 - 1 = no reframes due to framing bit errors.
Fs Bit Include. Only applicable in D4 mode (not ESF or SLC96). Setting this bit causes
errored Fs bits to be included as framing bit errors. A bad Fs bit will increment the Framing
Error Bit Counter, and will potentially cause a reframe (if it is the second bad framing bit out
of 5). The Fs bit of the receive frame 12 will only be included if D4SECY is set low.
Reframe. Setting this bit causes an automatic reframe (Must be manually set back to 0
before another reference can be issued).
MultiFrame Reframe. Only applicable in D4 or SLC96 mode. Setting this bit causes an
automatic multiframe reframe. The signaling bits are frozen until multiframe synchronization
is achieved. Terminal frame synchronization is not affected.
ESFYEL
D4YEL
Name
TxAO
Table 22 - Transmit Alarm Control Word (T1)
Table 21 - Framing Mode Select (T1)
ESFYellow Alarm. Setting this bit while in ESF mode causes a repeating
pattern of eight 1’s followed by eight 0’s to be insert onto the transmit FDL
(JTS bit set low - see Data Link Control Word) or sixteen 1’s (Japan
Telecom bit set high).
Transmit Secondary D4 Yellow Alarm. Setting this bit (in D4 mode)
causes the S bit of transmit frame 12 to be set.
D4 Yellow Alarm. When set bit 2 of all DS0 channels are forced low.
Transmit All Ones. When low, this control bit forces a framed or
unframed (depending on the state of Transmit Alarm Control bit 0) all ones
to be transmit at TTIP and TRING.
(Page 1, Address 10H)
(Page 1, Address 11H)
Zarlink Semiconductor Inc.
MT9074
Functional Description
62
Functional Description
Data Sheet