mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 41

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

Below is an example of the transmission of a three byte packet (’AA’ ’03’ ’77’ hex) (Interframe time fill). TXcen can
be enabled before or after this sequence.
(a) Write ’04’hex to Control Register 1
(b) Write ’AA’ hex to TX FIFO
(c) Write ’03’hex to TX FIFO
(d) Write ’34’hex to Control Register 1
(e) Write ’77’hex to TX FIFO
The transmitter may be enabled independently of the receiver. This is done by setting the TXEN bit of the Control
Register. Enabling happens immediately upon writing to the register. Disabling using TXen will occur after the
completion of the transmission of the present packet; the contents of the FIFO are not cleared. Disabling will consist
of stopping the transmitter clock. The Status and Interrupt Registers may still be read and the FIFO and Control
Registers may be written to while the transmitter is disabled. The transmitted FCS may be inhibited using the Tcrci
bit of Control Register 2. In this mode the opening flag followed by the data and closing flag is sent and zero
insertion still included, but no CRC. That is, the FCS is injected by the microprocessor as part of the data field. This
is used in V.120 terminal adaptation for synchronous protocol sensitive UI frames.
HDLC Receiver
After initialization and enabling, the receiver clocks in serial data, continuously checking for Go-aheads (0 1111
1110), flags (0111 1110), and Idle Channel states (at least fifteen ones). When a flag is detected, the receiver
synchronizes itself to the serial stream of data bits, automatically calculating the
flags after zero removal is less than 25 bits, then the packet is ignored so no bytes are loaded into Rx
the data length after zero removal is between 25 and 31 bits, a first byte and bad
FIFO
the
If address recognition is required, the Receiver Address Recognition Registers are loaded with the desired address
and the Adrec bit in the Control Register 1 is set high. Bit 0 of the Address Registers is used as an enable bit for
that byte, thus allowing either or both of the first two bytes to be compared to the expected values. Bit 0 of the first
byte of the address received (address extension bit) will be monitored to determine if a single or dual byte address
is being received. If this bit is 0 then a two byte address is being received and then only the first six bits of the first
address byte are compared. An all call condition is also monitored for the second address byte; and if received the
first address byte is ignored (not compared with mask byte). If the address extension bit is a 1 then a single byte
address is being received. In this case, an all call condition is monitored for in the first byte as well as the mask byte
written to the comparison register and the second byte is ignored. Seven bits of address comparison can be
realized on the first byte if this is a single byte address by setting the Seven bit of Control Register 2.
The following two Status Register bits (RQ8 and RQ9) are appended to each data byte as it is written to the Rx
FIFO. They indicate that a good packet has been received (good FCS and no frame abort), or a bad packet with
either incorrect FCS or frame abort. The Status and Interrupt Registers should be read before reading the Rx FIFO
since status and interrupt information correspond to the byte at the output of the FIFO (i.e., the byte about to be
read). The Status Register bits are encoded as follows:
RQ9
1
0
1
0
HEX
-Mark idle bit set
-Data byte
-Data byte
-TXEN; EOP; Mark idle bits set
-Final data byte
(see definition of RQ8 and RQ9 below). For an error-free packet, the result in the
pattern of ’F0B8’ when a closing flag is detected.
RQ8
1
1
0
0
last byte (good packet)
last byte (bad packet)
packet byte
Byte status
first byte
Zarlink Semiconductor Inc.
MT9074
41
FCS
FCS
. If the data length between
code are loaded into the Rx
CRC
register should match
Data Sheet
FIFO.
When