mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 44

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

MT9074
Data Sheet
When the C4b and the E1.5o clocks are not phase-locked, the rate at which data is being written into the slip buffer
from the DS1 side may differ from the rate at which it is being read out onto the ST-BUS. If this situation persists,
the delay limits stated in the previous paragraph will be violated and the slip buffer will perform a controlled frame
slip. That is, the buffer pointers will be automatically adjusted so that a full DS1 frame is either repeated or lost. All
frame slips occur on frame boundaries.
The minimum delay through the receive slip buffer is approximately 1 usec and the maximum delay is
approximately 249 uS. Figure 13 illustrates the relationship between the read and write pointers of the receive slip
buffer (contiguous time slot mapping). Measuring clockwise from the write pointer, if the read page pointer comes
within 8 usec of the write page pointer a frame slip will occur, which will put the read page pointer 157 usec from the
write page pointer. Conversely, if the read page pointer moves more than 249 usec from the write page pointer, a
slip will occur, which will put the read page pointer 124 usec from the write page pointer. This provides a worst case
hysteresis of 92 usec peak = 142 U.I.
The RSLIP and RSLPD status bits (page 3H, address 13H, bits 7 and 6 respectively) give indication of a receive
slip occurrence and direction. A maskable interrupt RxSLPI (page 1H, address 1BH, bit 0 - set high to mask) is also
provided. RSLIP changes state in the event of a slip. If RSLPD=0, the slip buffer has overflowed and a frame was
lost; if RSLPD=1, an underflow condition occurred and a frame was repeated
Slip Buffer in E1 Mode
In E1 mode, in addition to the elastic buffer in the jitter attenuator(JA), another elastic buffer (two frames deep) is
present, attached between the receive side and the ST-BUS (or GCI Bus) side of the MT9074 in E1 mode. This
elastic buffer is configured as a slip buffer which absorbs wander and low frequency jitter in multi-trunk applications.
The received PCM30 data is clocked into the slip buffer with the E1.5o clock and is clocked out of the slip buffer
with the C4b clock. The E1.5o extracted clock is generated from, and is therefore phase-locked with, the receive
PCM30 data. In normal operation, the C4b clock will be phase-locked to the E1.5o clock by a phase locked loop
(PLL). Therefore, in a single trunk system the receive data is in phase with the E1.5o clock, the C4b clock is
phase-locked to the E1.5o clock, and the read and write positions of the slip buffer will remain fixed with respect to
each other.
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Zarlink Semiconductor Inc.