mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 60

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

MT9074
Data Sheet
HDLC Interrupt Masks
Bit 7
Bit 0
Ga
EOPD TEOP
EopR
TxFl
FATxU
RxFf
RxOv
Digital Framer Mode
T1 Mode
Setting bit 4 in the Configuration Control Word (address 10H of Master Control Page 2) disables the LIU and
converts the MT9074 into a digital T1 transceiver. The digital 2.048 Mb/s ST-BUS backplane maps into transmit and
receive digital 1.544 Mb/s streams. The 1.544 Mb/s transmit streams may be formatted for single phase NRZ (by
setting bit 7 of the LIU Control Word - Master Page 1 high) or two phase NRZ. The data rate conversion (between
2.048 Mb/s and 1.544 Mb/s) is done within the MT9074. The transmit 1.544 MHz clock is internally generated from
a PLL that locks onto the input C4b clock. This clock is then output on pin E1.5o (PLCC pin 44 - QFP pin 32). The
digital 1.544 Mb/s transmit data is output on pins TXA and TXB (PLCC pins 37,38 - QFP pins 18,19) with the rising
edge of C1.5o. Receive digital data is clocked in on pins RRING and RTIP. This data is clocked in with the rising
edge of the input 1.544 MHz clock S/FR/E1.5i (PLCC pin 66, QFP pin 63). Coding is optional under software
control.
E1 Mode
Setting bit 4 in the Configuration Control Word (address 10H of Master Control Page 2) disables the LIU and
converts the MT9074 into a digital E1 transceiver. The digital 2.048 Mb/s ST-BUS backplane maps into transmit and
receive digital 2.048 Mb/s streams. The 2.048 Mb/s transmit data streams may be formatted for single phase NRZ
(by setting bit 7 of the LIU Control Word - Master Page 1 high) or two phase NRZ. The transmit 2.048 MHz clock is
derived from the input C4b clock. This clock is then output on pin E1.5o (PLCC pin 44 - QFP pin 32). The digital
2.048 Mb/s transmit data is output on pins TXA and TXB (PLCC pins 37,38 - QFP pins 18,19) with the rising edge
of E1.5o. Receive digital data is clocked in on pins RRING and RTIP. This data is clocked in with the rising edge of
the input 2.048 Mhz clock MS/FR/E1.5i (PLCC pin 66, QFP pin 63). Coding is optional under software control.
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Zarlink Semiconductor Inc.