mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 38

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

In E1 mode, when connected to the Data Link (DL) HDLC0 will operate at a selected bit rate of 4, 8, 12, 16 or 20
kbits/sec. HDLC0 can be selected by setting the control bit HDLC0 (page 01H, address 12H). When this bit is zero
all interrupts from HDLC0 are masked. For more information refer to following sections.
HDLC1 Functions
In T1 mode, DS1 channel 24 can be connected to HDLC1, operating at 56 or 64 Kb/s. HDLC1 can be activated by
setting the control bit HDLC1 (page 01H, address 12H). Setting control bit H1R64 (address 12 H on page 01H) high
selects 64 Kb/s operation for HDLC1. Setting this bit low selects 56 Kb/s for HDLC1. Interrupts from HDLC1 are
masked when it is disconnected.
In E1 mode, this controller may be connected to time slot 16 under Common Channel Signaling (CCS) mode. It
should be noted that the AIS16S function will always be active and the TAIS16 (page 01H, address 11h) function
will override all other transmit signaling.
HDLC1 can be selected by setting the control bit HDLC1. When this bit is zero all interrupts from HDLC1 are
masked.
HDLC Description
The HDLC handles the bit oriented packetized data transmission as per X.25 level two protocol defined by ITU-T. It
provides flag and abort sequence generation and detection, zero insertion and deletion, and Frame Check
Sequence (FCS) generation and detection. A single byte, dual byte and all call address in the received frame can
be recognized. Access to the receive FCS and inhibiting of transmit FCS for terminal adaptation are also provided.
Each HDLC controller has a 128 byte deep FIFO associated with it. The status and interrupt flags are
programmable for FIFO depths that can vary from 16 to 128 bytes in steps of 16 bytes. These and other features
are enabled through the HDLC control registers on page 0BH and 0CH.
HDLC Frame structure
In T1 mode or E1 mode, a valid HDLC frame begins with an opening flag, contains at least 16 bits of address and
control or information, and ends with a 16 bit FCS followed by a closing flag. Data formatted in this manner is also
referred to as a “packet”. Refer to Table 17: HDLC Frame Format.
All HDLC frames start and end with a unique flag sequence “01111110”. The transmitter generates these flags and
appends them to the packet to be transmitted. The receiver searches the incoming data stream for the flags on a
bit- by-bit basis to establish frame synchronization.
The data field consists of an address field, control field and information field. The address field consists of one or
two bytes directly following the opening flag. The control field consists of one byte directly following the address
field. The information field immediately follows the control field and consists of N bytes of data. The HDLC does not
distinguish between the control and information fields and a packet does not need to contain an information field to
be valid.
The FCS field, which precedes the closing flag, consists of two bytes. A cyclic redundancy check utilizing the
CRC-CCITT standard generator polynomial “X
calculated on all bits of the address and data field. The complement of the FCS is transmitted, most significant bit
first, in the FCS field. The receiver calculates the FCS on the incoming packet address, data and FCS field and
compares the result to “F0B8”. If no transmission errors are detected and the packet between the flags is at least 32
bits in length then the address and data are entered into the receive FIFO minus the FCS which is discarded.
Flag (7E)
One Byte
01111110
Table 17 - HDLC Frame Format
16
Zarlink Semiconductor Inc.
Data Field
+X
n Bytes
n
12
MT9074
≥
+X
2
38
5
+1” produces the 16-bit FCS. In the transmitter the FCS is
Bytes
FCS
Two
Flag (7E)
One Byte
01111110
Data Sheet