mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 127

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

7 - 0
Bit
Bit
7
6
5
4
3
2
1
0
Mark-Idle
ADREC
Name
FRUN
RxEN
BIT7-0
TxEN
Name
EOP
FA
TR
Table 144 - HDLC Control register 1
Table 143 - RX FIFO Read Register
When high this bit will enable address recognition. This forces the receiver
to recognize only those packets having the unique address as
programmed in the Receive Address Recognition Registers or if the
address is an All call address.
When low this bit will disable the HDLC receiver. The receiver will disable
after the rest of the packet presently being received is finished. The
receiver internal clock is disabled.
When high the receiver will be immediately enabled and will begin
searching for flags, Go-aheads etc.
When low this bit will disable the HDLC transmitter. The transmitter will
disable after the completion of the packet presently being transmitted. The
transmitter internal clock is disabled.
When high the transmitter will be immediately enabled and will begin
transmitting data, if any, or go to a mark idle or interframe time fill state.
Forms a tag on the next byte written the TX FIFO, and when set will
indicate an end of packet byte to the transmitter, which will transmit an
FCS following this byte. This facilitates loading of multiple packets into TX
FIFO. Reset automatically after a write to the TX FIFO occurs.
Forms a tag on the next byte written to the TX FIFO, and when set will
indicate to the transmitter that it should abort the packet in which that byte
is being transmitted. Reset automatically after a write to the TX FIFO.
When low, the transmitter will be in an idle state. When high it is in an
interframe time fill state. These two states will only occur when the TX
FIFO is empty.
When high this bit will enable transparent mode. This will perform the
parallel to serial conversion without inserting or deleting zeros. No CRC
bytes are sent or monitored nor are flags or aborts. A falling edge of TxEN
for transmit and a falling edge of RxEN for receive is necessary to initialize
transparent mode. This will also synchronize the data to the transmit and
receive channel structure. Also, the transmitter must be enabled through
control register 1 before transparent mode is entered.
When high the HDLC TX and RX are continuously enabled providing the
RxEN and TxEN bits are
This is the received data byte read from the RX FIFO. The status bits of
this byte can be read from the status register. The FIFO status is not
changed immediately when a write or read occurs. It is updated after the
data has settled and the transfer to the last available position has finished.
(Page B & C, Address 12H)
(Page B & C, Address 13H)
Zarlink Semiconductor Inc.
MT9074
127
Functional Description
set.
Functional Description
Data Sheet