mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 37

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

Data Link Operation in T1 Mode
SLC-96 and ESF protocol allow for carrier messages to be embedded in the overhead bit position. The MT9074
provides 3 separate means of controlling these data links. See Data Link and Rx Equalization Control Word -
address 12H, page 1H.
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External Data Link
In T1 mode MT9074 has two pairs of pins (TxDL and TxDLCLK, RxDL and RxDLCLK) dedicated to transmitting and
receiving bits in the selected overhead bit positions. Pins TxDLCLK and RxDLCLK are clock outputs available for
clocking data into the MT9074 (for transmit) or external device (for receive information). Each clock operates at 4
Khz. In the SLC-96 mode the optional serial data link is multiplexed into the Fs bit position. In the ESF mode the
serial data link is multiplexed into odd frames, i.e. the FDL bit positions.
Bit - Oriented Messaging
In T1 mode MT9074 Bit oriented messaging may be selected by setting bit 6 (BIOMEn) in the Data Link Control
Word (page 1H, address 12H). The transmit data link will contain the repeating serial data stream
111111110xxxxxx0 where the byte 0xxxxxx0 originates from the user programmed register "Transmit Bit Oriented
Message" - page 1H address 13H. The receive BIOM register "Receive Bit Oriented Message" - page 3H, address
15H, will contain the last received valid message (the 0xxxxxx0 portion of the incoming serial bit stream). To
prevent spurious inputs from creating false messages, a new message must be present in 7 of the last 10
appropriate byte positions before being loaded into the receive BIOM register. When a new message has been
received, a maskable interrupt (maskable by setting bit 1 low in Interrupt Mask Word Three - page 1H, address
1EH) may occur.
Dual HDLC
MT9074 has two embedded HDLC controllers (HDLC0, HDLC1) each of which includes the following features:
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HLDC0 Functions
In T1 mode, ESF Data Link (DL) can be connected to internal HDLC0, operating at a bit rate of 4 kbits/sec. HDLC0
can be activated by setting the control bit 5, address 12H in Master Control Page 0. Interrupts from HDLC0 are
masked when it is disconnected.
The data links (transmit and receive) may be sourced (sunk) from an external controller using dedicated pins
on the MT9074 in T1 mode (enabled by setting the bit 7 - EDL of the Data link Control Word).
Bit - Oriented Messages may be transmit and received via a dedicated TxBOM register (page 1H, address
13H) and a RxBOM (page 3H, address 15H). Transmission is enabled by setting bit 6 - BIOMEn in the Data
link Control Word. Bit - oriented messages may be periodically interrupted (up to once per second) for a
duration of up to 100 milliseconds. This is to accommodate bursts of message - oriented protocols. See
Table 16 for message structure.
An internal HDLC controller may be attached to the data link.
Independent transmit and receive FIFO's;
Receive FIFO maskable interrupts for nearly full (programmable interrupt levels) and overflow conditions;
Transmit FIFO maskable interrupts for nearly empty (programmable interrupt levels) and underflow
conditions;
Maskable interrupts for transmit end-of-packet and receive end-of-packet;
Maskable interrupts for receive bad-frame (includes frame abort);
Transmit end-of-packet and frame-abort functions
Zarlink Semiconductor Inc.
MT9074
37
Data Sheet