mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 31

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

The result of the comparison of the received CRC-4 remainder with the locally generated remainder will be
transported to the far end by the E-bits. Therefore, if E1 = 0, a CRC-4 error was discovered in a submultiframe 1
received at the far end; and if E2 = 0, a CRC-4 error was discovered in a submultiframe 2 received at the far end.
No submultiframe sequence numbers or re-transmission capabilities are supported with layer 1 PCM30 protocol.
See ITU-T G.704 and G.706 for more details on the operation of CRC-4 and E-bits.
There are two CRC multiframe alignment algorithm options selected by the AUTC control bit (address 10H, page
01H). When AUTC is zero, automatic CRC-to-non-CRC interworking is selected. When AUTC is one and ARAI is
low, if CRC-4 multiframe alignment is not found in 400 msec, the transmit RAI will be continuously high until CRC-4
multiframe alignment is achieved.
The control bit for transmit E bits (TE, address 11H of page 01H) will have the same function in both states of
AUTC. That is, when CRC-4 synchronization is not achieved the state of the transmit E-bits will be the same as the
state of the TE control bit. When CRC-4 synchronization is achieved the transmit E-bits will function as per ITU-T
G.704. Table 12 outlines the operation of the AUTC, ARAI and TALM control bits of the MT9074.
CAS Signaling Multiframing in E1 Mode
The purpose of the signaling multiframing algorithm is to provide a scheme that will allow the association of a
specific ABCD signaling nibble with the appropriate PCM30 channel. Time slot 16 is reserved for the
communication of Channel Associated Signaling (CAS) information (i.e., ABCD signaling bits for up to 30
channels). Refer to ITU-T G.704 and G.732 for more details on CAS multiframing requirements.
A CAS signaling multiframe consists of 16 basic frames (numbered 0 to 15), which results in a multiframe repetition
rate of 2 msec. It should be noted that the boundaries of the signaling multiframe may be completely distinct from
those of the CRC-4 multiframe. CAS multiframe alignment is based on a multiframe alignment signal (a 0000 bit
sequence), which occurs in the most significant nibble of time slot 16 of basic frame 0 of the CAS multiframe. Bit 6
of this time slot is the multiframe alarm bit (usually designated Y). When CAS multiframing is acquired on the
AUTC
0
0
0
1
1
1
ARAI
0
1
1
0
1
1
Table 12 - Operation of AUTC, ARAI and TALM Control Bits (E1 Mode)
TALM
X
X
0
1
0
1
Automatic CRC-interworking is activated. If no valid CRC MFAS is being
received, transmit RAI will flicker high with every reframe (8msec.), this cycle
will continue for 400 msec., then transmit RAI will be low continuously. The
device will stop searching for CRC MFAS, continue to transmit CRC-4
remainders, stop CRC-4 processing, indicate CRC-to-non-CRC operation
and transmit E-bits to be the same state as the TE control bit (page 01H,
address 16H).
Automatic CRC-interworking is activated. Transmit RAI is low continuously.
Automatic CRC-interworking is activated. Transmit RAI is high continuously.
Automatic CRC-interworking is de-activated. If no valid CRC MFAS is being
received, transmit RAI flickers high with every reframe (8 msec.), this cycle
continues for 400 msec, then transmit RAI becomes high continuously. The
device continues to search for CRC MFAS and transmit E-bits are the same
state as the TE control bit. When CRCSYN = 0, the CRC MFAS search is
terminated and the transmit RAI goes low.
Automatic CRC-interworking is de-activated. Transmit RAI is low
continuously.
Automatic CRC-interworking is de-activated. Transmit RAI is high
continuously.
Zarlink Semiconductor Inc.
MT9074
31
Description
Data Sheet