mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 131

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

7-0s
7-0
Bit
Bit
Bit
7
6
5
4
3
TxCNT7-0
CRC7-0
Name
Name
RTLOOP
CRCTST
Name
HRST
RSV
RSV
Table 151 - Transmit Byte Count Register
Table 152 - HDLC Test Control Register
Table 150 - Receive CRC LSB Register
The LSB byte of the CRC received from the transmitter. These bits are
as the transmitter sent them; that is, most significant bit first and inverted.
This register is updated at the end of each received packet and therefore
should be read when end of packet is detected.
Transmit Byte Count Register. The Transmit Byte Count Register
indicating the length of the packet about to be transmitted. When this
register reaches the count of one, the next write to the Tx FIFO will be
tagged as an end of packet byte. The counter decrements at the end of
the write to the Tx FIFO. If the Cycle bit of Control Register 2 is set high,
the counter will cycle through the programmed value continuously.
(Page B & C, Address 1AH)
(Page B & C, Address 1BH)
(Page B & C, Address 19H)
HDLC Reset. When this bit is set to one, the HDLC will be reset.
This is similar to RESET being applied, the only difference being
that this bit will not be reset. This bit can only be reset by writing a
zero twice to this location or applying RESET.
RT Loopback. When this bit is high, receive to transmit HDLC
loopback will be activated. Receive data, including end of packet
indication, but not including flags or CRC, will be written to the TX
FIFO as well as the RX FIFO. When the transmitter is enabled,
this data will be transmitted as though written by the
microprocessor. Both good and bad packets will be looped back.
Receive to transmit loopback may also be accomplished by
reading the RX FIFO using the microprocessor and writing these
bytes, with appropriate tags, into the TX FIFO.
Reserved. Must be set to 0 for normal operation.
Reserved. Must be set to 0 for normal operation.
CRC Remainder Test. This bit allows direct access to the CRC
Comparison Register in the receiver through the serial interface.
After testing is enabled, serial data is clocked in until the data
aligns with the internal comparison (16 RXC clock cycles) and
then the clock is stopped. The expected pattern is F0B8 hex. Each
bit of the CRC can be corrupted to allow more efficient testing.
Zarlink Semiconductor Inc.
MT9074
131
Functional Description
Functional Description
Functional Description
Data Sheet