mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 58

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

MT9074
Data Sheet
Pulse Density Violation Detect
In T1 mode bit 2 of address 11H on page 3H (PDV) toggles if the receive data fails to meet ones density
requirements. It will toggle upon detection of 16 consecutive zeros on the line data, or if there are less than N ones
in a window of 8(N+1) bits - where N = 1 to 23.
Timer Outputs
In T1 mode MT9074 has a one second timer derived from the 20 Mhz oscillator pins. The timer may be used to
trigger interrupts for T1.403/408 performance messaging.
E1 Mode
Consecutive Frame Alignment Patterns (CONFAP)
Two consecutive frame alignment signals in error.
Receive Frame Alignment Signals
These bits are received on the PCM30 and link in bit positions two to eight of time slot 0 - frame alignment signal.
These signals form the frame alignment signal and should be 0011011.
Receive Non Frame Alignment Signal
This signal is received on the PCM30 and link in bit position two of time slot 0 - non frame alignment signal.
Receive Multiframe Alignment Signals
These signal are received on the PCM30 and link in bit position one to four of time slot 16 of frame zero of every
signaling multiframe.
Interrupts
The MT9074 has an extensive suite of maskable interrupts, which are divided into four categories based on the
type of event that caused the interrupt. Each interrupt has an associated mask and interrupt bit. When an
unmasked interrupt event occurs, IRQ will go low and one or more bits of the appropriate interrupt register will go
high. After each interrupt register is read it is automatically cleared. When all interrupt registers are cleared IRQ will
return to a high impedance state. This function can also be accomplished by toggling the INTA bit (page 1, address
1AH).
All the interrupts of the MT9074 in T1 and E1 mode are maskable. This is accomplished through interrupt mask
words zero to three, which are located on page 1, addresses 1BH to 1EH and the (optional) HDLC interrupt mask
located at address 16 of page B.
After a MT9074 reset (RESET pin or RST control bit), all interrupts are masked.
All interrupts may be suspended, without changing the interrupt mask words, by making the SPND control bit of
page 1, address 1AH high.
All interrupts are cleared by forcing the pin TxAO low.
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