mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 77

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

4-0
Bit
Bit
4-0
Bit
7
6
5
0
7
6
5
RSLPD
RxFRM
RSLIP
Name
- - -
Name
LLDD
Name
1SEC
2SEC
5SEC
- - -
Table 48 - Most Significant Phase Status Word
Receive Slip. A change of state (i.e., 1-to-0 or 0-to-1) indicates that a receive
controlled frame slip has occurred.
Receive Slip Direction. If one, indicates that the last received frame slip
resulted in a repeated frame, i.e., the system clock (C4b) is faster than network
clock (E2o). If zero, indicates that the last received frame slip resulted in a lost
frame, i.e., system clock slower than network clock. Updated on an RSLIP
occurrence basis.
Receive Frame Delay. The most significant bit of the Receive Slip Buffer
Phase Status Word. If zero, the delay through the receive elastic buffer is
greater than one frame in length; if one, the delay through the receive elastic
buffer is less than one frame in length.
Unused
One Second Timer Status. This bit changes state once every 0.5 seconds.
Two Second Timer Status. This bit changes state once every second and
is synchronous with the 1SEC timer.
Five Second Timer Status. This bit changes state once every 2.5 seconds
and is synchronous with the 1SEC timer.
Unused.
Line Loopback Disable Detect. This bit will be set when a framed or
unframed repeating pattern of 001 has been detected during a 48
millisecond interval. Up to fifteen errors are permitted per integration
period.
Table 46 - Alarm Status Word
Table 47 - Timer Status Word
(Page 3, Address 11H) (T1)
(Page 3, Address 12H) (T1)
(Page 3, Address 13H) (T1)
Zarlink Semiconductor Inc.
MT9074
77
Functional Description
Functional Description
Functional Description
Data Sheet