mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet - Page 39

• Manufacturer Part Number: mt9074ap1
• Description: T1/e1/j1 Single Chip Transceiver With Wide Dynamic Range Liu
• Manufacturer: Zarlink Semiconductor

Data Transparency (Zero Insertion/Deletion)
Transparency ensures that the contents of a data packet do not imitate a flag, go-ahead, frame abort or idle
channel. The contents of a transmitted frame, between the flags, is examined on a bit-by-bit basis and a 0 bit is
inserted after all sequences of 5 contiguous 1 bits (including the last five bits of the FCS). Upon receiving five
contiguous 1s within a frame the receiver deletes the following 0 bit.
Invalid Frames
A frame is invalid if one of the following four conditions exists (Inserted zeros are not part of a valid count):
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Frame Abort
The transmitter will abort a current packet by substituting a zero followed by seven contiguous 1s in place of the
normal packet. The receiver will abort upon reception of seven contiguous 1s occurring between the flags of a
packet which contains at least 26 bits.
Note that should the last received byte before the frame abort end with contiguous 1s, these are included in the
seven 1s required for a receiver abort. This means that the location of the abort sequence in the receiver may occur
before the location of the abort sequence in the originally transmitted packet. If this happens then the last data
written to the receive FIFO will not correspond exactly with the last byte sent before the frame abort.
Interframe Time Fill and Link Channel States
When the HDLC transmitter is not sending packets it will wait in one of two states
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In both states the transmitter will exit the wait state when data is loaded into the transmitter FIFO.
Go-Ahead
A go ahead is defined as the pattern "011111110" (contiguous 7Fs) and is the occurrence of a frame abort sequence
followed by a zero, outside of the boundaries of a normal packet. Being able to distinguish a proper (in packet)
frame abort sequence from one occurring outside of a packet allows a higher level of signaling protocol which is not
part of the HDLC specifications.
HDLC Functional Description
The HDLC transceiver can be reset by either the power reset input signal or by the HRST Control bit in the test
control register (software reset). When reset, the HDLC Control Registers are cleared, resulting in the transmitter
and receiver being disabled. The Receiver and Transmitter can be enabled independent of one another through
Control Register 1. The transceiver input and output are enabled when the enable control bits in Control Register 1
are set. Transmit to receive loopback as well as a receive to transmit loopback are also supported. Transmit and
If the FCS pattern generated from the received data does not match the “F0B8” pattern then the last data
byte of the packet is written to the received FIFO with a ‘bad packet’ indication.
A short frame exists if there are less than 25 bits between the flags. Short frames are ignored by the receiver
and nothing is written to the receive FIFO.
Packets which are at least 25 bits in length but less than 32 bits between the flags are also invalid. In this
case the data is written to the FIFO but the last byte is tagged with a “bad packet” indication.
If a frame abort sequence is detected the packet is invalid. Some or all of the current packet will reside in the
receive FIFO, assuming the packet length before the abort sequence was at least 26 bits long.
Interframe Time Fill state: This is a continuous series of flags occurring between frames indicating that the
channel is active but that no data is being sent.
Idle state: An idle Channel occurs when at least 15 contiguous 1s are transmitted or received.
Zarlink Semiconductor Inc.
MT9074
39
Data Sheet