gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 123

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Datasheet—Intel
Table 62.
5.6.2.6
Figure 29.
Table 63.
August 2006
Document Number:
MDIO Timings Values
DDRI SDRAM Bus
DDRI SDRAM Write Timings
DDRI SDRAM Write Timings Values (Sheet 1 of 2)
®
Note:
1.
Notes:
1.
Symbol
306261-004US
Symbol
IXP45X and Intel
DDRI_DQ, _CB, _DM
T
T
T
T1
T2
T3
T4
T5
1
2
3
Timing was designed for a system load between 5pF and 20pF
DDRI_M_CLK is representative of all DDRI_CK and DDRI_CK_N signals. The rising edge of
DDRI_M_CLK represents the crossover point of the respective DDRI_CK and DDRI_CK_N signals.
The skew between the separate DDR clocks have been compensated in the timings which have been
described. The period to period clock jitter on each DDRI_M_CLK pair is spec’ed at +/-100ps.
DDRI_M_CLK
Output valid for DDRI_DQS prior to each edge of
DDRI_M_CLK.
DDRI_DQS output hold time after each edge of
the DDRI_M_CLK.
Output valid for ADDR/CTRL prior to the rising
edge of DDRI_M_CLK. Address and control
signals consist of DDRI_RAS_N, DDRI_CAS_N,
DDRI_CS_N, DDRI_WE_N, DDRI_BA, DDRI_MA,
and DDRI_CKE.
ETH_MDIO, clock to output timing with respect to
rising edge of ETH_MDC clock
ETH_MDIO output hold timing after the rising
edge of ETH_MDC clock
ETH_MDIO input setup prior to rising edge of
ETH_MDC clock
ETH_MDIO hold time after the rising edge of
ETH_MDC clock
ETH_MDC clock period
ADDR/CTRL
DDRI_DQS
®
IXP46X Product Line of Network Processors
Parameter
Parameter
Intel
®
IXP45X and Intel
T
1
T
2
®
Min.
125
Min.
2.5
10
IXP46X Product Line of Network Processors
3
1
ADDR/CMD VALID
T
DATA VALID
ETH_MDC/2
5
T
3
+ 15 ns
Max.
Max.
500
1.4
1.0
T
T
Units
4
6
Units
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
Datasheet
Notes
Notes
123