gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 132

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Table 70.
Table 71.
Intel
Datasheet
132
®
IXP45X and Intel
HPI* Timing Symbol Description
HPI*–8 Mode Write Accesses Values
Notes:
1.
2.
3.
4.
5.
6.
7.
T
T
T
T
T
Symbol
cs2hds1val
hds1_pulse
data_setup
add_setup
data_hold
State
T
®
recov
T1
T2
T3
T4
T5
IXP46X Product Line of Network Processors
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
IXP45X/IXP46X network processors have had sufficient time to recognize the HRDY and hold the
address phase for at least one clock pulse after the HRDY is de-active.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three
T clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the
IXP45X/IXP46X network processors have had sufficient time to recognize the HRDY and hold the
data setup phase for at least one clock pulse after the HRDY is de-active
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1
or T3 until HRDY is de-active
One cycle is the period of the Expansion Bus clock.
Timing was designed for a system load between 5 pF and 60 pF for high drive setting.
Valid time that address is asserted on the line. The
address is asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data
strobe being active.
Pulse width of the HDS1 data strobe
Data valid prior to the rising edge of the HDS1 data
strobe.
Data valid after the rising edge of the HDS1 data strobe.
Time required between successive accesses on the
expansion interface.
Intel
Setup/Chip Select Timing
®
IXP45X and Intel
Recovery Phase
Address Timing
Strobe Timing
Description
Hold Timing
Parameter
®
IXP46X Product Line of Network Processors—Datasheet
Min
3
3
2
3
2
Max
16
17
4
4
4
Min.
Document Number:
11
3
4
4
4
2
Cycles
Cycles
Cycles
Cycles
Cycles
Unit
Max.
45
36
17
4
5
5
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Units
1, 5, 6
2, 6
3, 5, 6
6
6
306261-004US
Notes
August 2006
1, 5,
5,
2, 4,
3, 5,
3,
4,
Notes
6
6
6
6
5
6