gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 26

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

3.1.9.2
3.1.10
3.1.11
Intel
Datasheet
26
®
IXP45X and Intel
Embedded Memory P30 synchronous-burst mode.
Byte-wide parity is an optional configuration of this interface in all modes of operation
except:
At the de-assertion of reset, the 25-bit address bus is used to capture configuration
information from the levels that are applied to the pins at this time. External pull-up/
pull-down resistors are used to tie the signals to particular logic levels. (For additional
details, see
a pull-up state during this initialization period, the IXP45X/IXP46X network processors
contain internal weak pull-ups. Depending upon the system design, pull-down resistors
may be the only thing required.
High-Speed, Serial Interfaces
Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs
to the IXP45X/IXP46X network processors. The high-speed, serial interfaces are
capable of supporting various protocols, based on the implementation of the code
developed for the network processor engine.
For a list of supported protocols, see the Intel
Expansion Bus Enhanced Mode of Operation
In the enhanced mode of operation, the expansion interface is a 32-bit interface that
allows an address range of 512 bytes to 32 Mbytes per chip select on IXP45X/IXP46X
network processors, using 25 address lines for each of the eight independent chip
selects.
Additionally, in enhanced mode, the interface supports shared access to the bus with
external masters. This shared access is achieved with four request/grant pins and an
integrated arbiter. Not only can external devices access each other, but they can also
access the IXP45X/IXP46X network processors’ internal registers (including the DDRI
SDRAM interface).
The advantage to this feature is that shared memory access can be achieved by using
the DDRI SDRAM interface attached to IXP45X/IXP46X network processors. This lowers
the system’s overall bill of materials.
Enhanced mode also supports synchronous transfers at speeds of up to 80 MHz with a
40-pF load. In addition to fully synchronous support, the enhanced mode also supports
burst transfers of up to eight-word lengths. The synchronous bus support is compatible
to Zero Bus Turnaround (ZBT) SRAM cycles for inbound/outbound transactions for both
read/write transactions.
Additionally, the outbound read transactions can support the Intel StrataFlash
The high-speed, serial interfaces (HSS) are six-signal interfaces that support serial
transfer speeds from 512 KHz to 8.192 MHz, for some models of the IXP45X/IXP46X
network processors. (For processor-specific speeds, see
UARTs
The UART interfaces are a 16550-compliant UART with the exception of transmit and
receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes
required by the 16550 UART specification.
• Intel StrataFlash
• HPI mode
®
IXP46X Product Line of Network Processors
“Package Information” on page
Intel
®
®
IXP45X and Intel
Embedded Memory P30 synchronous-burst mode
®
IXP46X Product Line of Network Processors—Datasheet
37.) If a signal is required to be placed into
®
IXP400 Software Programmer’s Guide.
Table 3 on page
Document Number:
18.)
306261-004US
August 2006
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