gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 134

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Figure 38.
Table 74.
Intel
Datasheet
134
®
IXP45X and Intel
HPI*-16 Multiplexed Write Mode
HPI*-16 Multiplexed Read Accesses Values
EX_ADDR[2:1]
Notes:
1.
2.
3.
4.
5.
6.
7.
T
T
T
T
Symbol
cs2hds1val
hds1_pulse
data_setup
add_setup
EX_RDY_N
T
EX_W R_N
®
EX_CS_N
EX_RD_N
EX_DATA
recov
(hr_w_n)
(hds1_n)
EX_CLK
IXP46X Product Line of Network Processors
(hcs_n)
(hcntl)
(hrdy)
(hdin)
Tcs2hds1val
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
IXP45X/IXP46X network processors have had sufficient time to recognize the HRDY and hold the
address phase for at least one clock pulse after the HRDY is de-active.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three
T clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the
IXP45X/IXP46X network processors have had sufficient time to recognize the HRDY and hold the
data setup phase for at least one clock pulse after the HRDY is de-active
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active
One cycle is the period of the Expansion Bus clock.
Timing was designed for a system load between 5pF and 60pF for high drive setting
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data
strobe being active.
Pulse width of the HDS1 data strobe
Data is valid from the time from of the falling edge of
HDS1_N to when the data is read.
Time required between successive accesses on the
expansion interface.
Intel
T1
®
Tdata_setup
Thds1_pulse
IXP45X and Intel
T2
Parameter
Tadd_setup
T3
Valid
Data
®
Tdata_hold
IXP46X Product Line of Network Processors—Datasheet
T4
Trecov
T5
T1 T2
Document Number:
Min.
11
3
4
4
2
Max.
45
17
4
5
5
Valid
T3
Data
Cycles
Cycles
Cycles
Cycles
cycles
Units
306261-004US
August 2006
Notes
1, 5,
5,
2, 4,
3, 5,
4,
T4
6
6
6
5
6