gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 67

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 16.
August 2006
67
EX_CS_N[7:0]
EX_DATA[31:0]
EX_BE_N[3:0]
EX_IOWAIT_N
EX_RDY_N[3:0]
EX_PARITY[3:0]
Note:
†
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Table 1 on page
Expansion Bus Interface (Sheet 2 of 3)
Reset
Power
on
H
H
H
H
Z
Z
†
13.
Reset
VI
VI
H
H
H
H
†
Software
Enables
Normal
Table 8 on page
Reset
After
Until
VB
VB
VB
VB
VI
VI
Software
Configur
Possible
Enables
ations
After
VB
VB
VB
VB
VI
VI
43.
®
IXP45X and Intel
Type
I/O
I/O
I/O
I/O
I
I
†
Used to drive chip selects for outbound transactions for the expansion bus.
Expansion bus, bidirectional data
Expansion bus Byte enables. EX_BE_N is used to select the particular bytes that will be written or
read when executing outbound transfers.
When executing inbound transfers, EX_BE_N will be used to select sub-word writes. Only 32 bit
reads of the expansion bus is supported when operating on inbound transfers.
EX_BE_N is driven by the IXP45X/IXP46X network processors unless grant is asserted to an
external master.
Data ready/acknowledge from expansion bus devices. Expansion bus access is halted when an
external device sets EX_IOWAIT_N to logic 0 and resume from the halted location once the external
device sets EX_IOWAIT_N to logic 1. This signal affects accesses that use EX_CS_N[7:0] when the
chip select is configured in Intel and Motorola modes of operation.
During idle cycles, the board is responsible for ensuring that EX_IOWAIT_N is pulled-up.
Additionally, EX_IOWAIT_N must always be pulled high during Micron ZBT, Intel Synchronous Mode,
and HPI cycles
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.
HPI interface ready signals. Can be configured to be active high or active low. These signals are
used to halt accesses using Chip Selects 7 through 4 when the chip selects are configured to
operate in HPI mode. There is one RDY signal per chip select. This signal only affects accesses that
use EX_CS_N[7:4].
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.
Byte wide parity protection on the EX_DATA[31:0]
• Chip selects 0 through 7 can be configured to support Intel/Intel Synchronous/Motorola/ZBT
• Chip selects 4 through 7 can be configured to support TI HPI bus cycles.
• These signal are also sampled by the arbiter to determine when to arbitrate. Driving the signals
• External board pull-ups are required on EX_CS_N to ensure this signal remains deasserted
®
SRAM bus cycles.
from an external interface has no effect on the operation of anything but the arbiter.
(especially in a multi-master environment). Additionally, the system designer is responsible for
ensuring that all the tri-stated signals do not become indeterminate. If they become
indeterminate, excessive power consumption will occur in the PAD input buffers.
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
Intel
®
IXP45X and Intel
Description
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-004US