gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 54

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 14.
August 2006
54
UTP_OP_DATA[4] /
ETHA_TXEN
UTP_OP_DATA[6:5]
UTP_OP_DATA[7] /
SMII_TXDATA[4]
UTP_OP_ADDR[4:0]
Note:
†
††
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
For information on selecting the desired interface, see the Intel
Table 1 on page
UTOPIA Level 2/MII_A/ SMII Interface (Sheet 2 of 7)
Reset
Power
on
Z
Z
Z
Z
13.
†
Reset
Z
Z
Z
Z
†
Table 8 on page
Software
Enables
Normal
Reset
After
Until
Z
Z
Z
Z
Software
Configur
Possible
Enables
ations
After
43.
VO
VO
VO
VO
®
IXP45X and Intel
®
Type
TRI
TRI
TRI
I/O
IXP45X and Intel
†
UTOPIA Mode of Operation:
UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the
ATM UTOPIA Level 2-compliant PHY.
MII Mode of Operation:
Indicates that the PHY is being presented with nibbles on the MII interface. Asserted
synchronously, with respect to ETHA_TXCLK, at the first nibble of the preamble, and remains
asserted until all the nibbles of a frame are presented. This MAC does not contains hardware
hashing capabilities local to the interface.
SMII mode of operation:
Not used.
UTOPIA Mode of Operation:
UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the
ATM UTOPIA Level 2-compliant PHY.
UTOPIA Mode of Operation:
UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the
ATM UTOPIA Level 2-compliant PHY.
MII Mode of Operation:
Not used.
SMII mode of operation:
Output data for SMII interface number four. The data on this signal is transmitted synchronously
with respect to the rising edge of SMII_CLK when operating as an SMII interface and
synchronously with respect to the rising edge of SMII_TXCLK when operating as a Source
Synchronous SMII interface
Transmit PHY address bus. Used by the processor when operating in MPHY mode to poll and select
a single PHY at any given time.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA
and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel
IXP45X and Intel
being used in a system design, this interface/signal is not required for any connection.
®
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
®
IXP46X Product Line of Network Processors Developer’s Manual.
®
Intel
IXP46X Product Line of Network Processors Developer’s Manual) and is not
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
processor
processor
processor
306261-004US
®
to an
to an
to an