gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 51

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 12.
Table 13.
August 2006
51
HSS_RXDATA0
HSS_RXCLK0
Note:
†
HSS_TXFRAME1
HSS_TXDATA1
Note:
†
Name
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Table 1 on page
Table 1 on page
High-Speed, Serial Interface 0 (Sheet 2 of 2)
High-Speed, Serial Interface 1 (Sheet 1 of 2)
Power
Reset
Reset
Power
on
on
Z
Z
Z
Z
13.
13.
†
†
Reset
Reset
VI
Z
Z
Z
†
†
Software
Table 8 on page
Software
Table 8 on page
Enables
Enables
Normal
Normal
Reset
Reset
After
After
Until
Until
VOD
VB
VB
VI
Software
Configur
Software
Possible
Configur
Enables
Possible
Enables
ations
ations
After
After
VOD
VB
VI
43.
VB
43.
®
®
IXP45X and Intel
IXP45X and Intel
Type
Type
I/O
I/O
OD
I
†
†
Receive data input. Can be sampled on the rising or falling edge of the receive clock.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the HSS soft
fuse (refer to Expansion Bus Controller chapter of the Intel
Line of Network Processors Developer’s Manual) and is not being used in a system design, this
interface/signal is not required for any connection.
The High-Speed Serial (HSS) receive clock signal can be configured as an input or an output. The
clock can be from 512 KHz to 8.192 MHz. Used to sample the received data. Configured as an
input upon reset.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
The High-Speed Serial (HSS) transmit frame signal can be configured as an input or an output to
allow an external source to be synchronized with the transmitted data. Often known as a Frame
Sync signal. Configured as an input upon reset.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the HSS soft
fuse (refer to Expansion Bus Controller chapter of the Intel
Line of Network Processors Developer’s Manual) and is not being used in a system design, this
interface/signal is not required for any connection.
Transmit data out. Open Drain output.
When this interface/signal is enabled and either used or unused in a system design, it should be
pulled high with a 10-KΩ resistor to V
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
®
®
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
Intel
®
IXP45X and Intel
CCP
. When this interface is disabled via the HSS soft fuse
Description
®
Description
IXP46X Product Line of Network Processors Datasheet
®
IXP45X and Intel
®
®
IXP45X and Intel
IXP45X and Intel
Document Number:
®
IXP46X Product Line of
®
®
IXP46X Product
IXP46X Product
306261-004US