gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 52

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 13.
August 2006
52
HSS_TXCLK1
HSS_RXFRAME1
HSS_RXDATA1
HSS_RXCLK1
Note:
†
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Table 1 on page
High-Speed, Serial Interface 1 (Sheet 2 of 2)
Reset
Power
on
Z
Z
Z
Z
13.
†
Reset
VI
Z
Z
Z
†
Software
Table 8 on page
Enables
Normal
Reset
After
Until
VB
VB
VB
VI
Software
Configur
Possible
Enables
ations
After
VB
VB
VB
43.
VI
®
IXP45X and Intel
Type
I/O
I/O
I/O
I
†
The High-Speed Serial (HSS) transmit clock signal can be configured as an input or an output. The
clock can be a frequency ranging from 512 KHz to 8.192 MHz. Used to clock out the transmitted
data. Configured as an input upon reset. Frame sync and Data can be selected to be generated on
the rising or falling edge of the transmit clock.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
The High-Speed Serial (HSS) receive frame signal can be configured as an input or an output to
allow an external source to be synchronized with the received data. Often known as a Frame Sync
signal. Configured as an input upon reset.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the HSS soft
fuse (refer to Expansion Bus Controller chapter of the Intel
Line of Network Processors Developer’s Manual) and is not being used in a system design, this
interface/signal is not required for any connection.
Receive data input. Can be sampled on the rising or falling edge of the receive clock.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the HSS soft
fuse (refer to Expansion Bus Controller chapter of the Intel
Line of Network Processors Developer’s Manual) and is not being used in a system design, this
interface/signal is not required for any connection.
The High-Speed Serial (HSS) receive clock signal can be configured as an input or an output. The
clock can be from 512 KHz to 8.192 MHz. Used to sample the received data. Configured as an
input upon reset.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
®
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
Intel
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
®
®
IXP45X and Intel
IXP45X and Intel
Document Number:
®
®
IXP46X Product
IXP46X Product
306261-004US