gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 49

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 11.
August 2006
49
PCI_REQ_N[0]
PCI_GNT_N[3:1]
PCI_GNT_N[0]
PCI_INTA_N
PCI_CLKIN
Note:
†
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Table 1 on page
PCI Controller (Sheet 4 of 4)
Power
Reset
on
Z
Z
Z
Z
Z
†
13.
Reset
VI
Z
Z
Z
Z
†
Software
Enables
Normal
Table 8 on page
Reset
After
Until
VO
VO
VI
VI
Z
Software
Configur
Possible
Enables
VI / VO
VI / VO
ations
After
VOD
VO
VI
43.
®
IXP45X and Intel
Type
O/D
I/O
I/O
O
I
†
PCI arbitration request:
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI arbitration grant: Generated by the internal PCI arbiter to allow an agent to claim control of the
PCI bus.
PCI arbitration grant:
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI interrupt: Used to request an interrupt.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI Clock: Clock provides timing for all transactions on PCI. All PCI signals — except INTA#, INTB#,
INTC#, and INTD# — are sampled on the rising edge of CLK and timing parameters are defined
with respect to this edge. The PCI clock rate can operate at up to 66 MHz.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor.
• When configured as an input (PCI arbiter enabled), the internal PCI arbiter will allow an agent
• When configured as an output (PCI arbiter disabled), the pin will be used to request access to
• When configured as an output (PCI arbiter enabled), the internal PCI arbiter to allow an agent
• When configured as an input (PCI arbiter disabled), the pin will be used to claim access of the
®
to request the PCI bus.
the PCI bus from an external arbiter.
to claim control of the PCI bus.
PCI bus from an external arbiter.
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
Intel
®
IXP45X and Intel
Description
®
IXP46X Product Line of Network Processors Datasheet
®
®
®
IXP45X and Intel
IXP45X and Intel
IXP45X and Intel
Document Number:
®
®
®
IXP46X Product Line of
IXP46X Product Line of
IXP46X Product Line of
306261-004US