gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 29

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Datasheet—Intel
3.1.16
Note:
3.1.17
3.1.18
August 2006
Document Number:
IEEE 1588 Hardware Assistance
In a distributed control system containing multiple clocks, individual clocks tend to drift
apart. Some kind of correction mechanism is necessary to synchronize the individual
clocks to maintain global time, which is accurate to some clock resolution. The
IEEE 1588 standard for a precision clock synchronization protocol for networked
measurement and control systems can be used for this purpose. The IEEE 1588
standard defines several messages that can be used to exchange timing information.
The IXP45X/IXP46X network processors implement the IEEE 1588 hardware-assist
logic on three of the MII interfaces. Using the hardware assist logic along with software
running on the Intel XScale
compliant network node can be implemented.
The IXP455 network processor does not support IEEE 1588 hardware-assist.
Synchronous Serial Port Interface
The IXP45X/IXP46X network processors have a dedicated Synchronous Serial Port
(SSP) interface. The SSP interface is a full-duplex synchronous serial interface. It can
connect to a variety of external analog-to-digital (A/D) converters, audio and telecom
CODECs, and many other devices which use serial protocols for transferring data.
It supports National’s Microwire*, Texas Instruments’* synchronous serial protocol
(SSP), and Motorola's* serial peripheral interface (SPI*) protocol.
The SSP operates in master mode (the attached peripheral functions as a slave), and
supports serial bit rates from 7.2 Kbps to 1.8432 Mbps using the on-chip, 3.6864-MHz
clock, and bit rates from 65.10 Kbps to 16.67 Mbps using a maximum off-chip, 33.33
MHz clock. Serial data formats may range from 4 to 16 bits in length. Two on-chip
register blocks function as independent FIFOs for data, one for each direction. The
FIFOs are 16 entries deep x 16 bits wide. Each 32-bit word from the system fills one
entry in a FIFO using the lower half 16-bits of a 32-bit word.
I
The I
master and slave device residing on the I
SDA is the data pin for input and output functions and SCL is the clock pin for reference
and control of the I
The I
peripherals and micro-controllers for system management functions. The serial bus
requires a minimum of hardware for an economical system to relay status and
reliability information on the IXP45X/IXP46X network processors subsystem to an
external device.
The I
network processors’ APB. Data is transmitted to and received from the I
buffered interface. Control and status information is relayed through a set of memory-
mapped registers. Refer to the I
operation.
The I
®
2
• Multi-master capabilities
• Slave capabilities
306261-004US
IXP45X and Intel
C Interface
2
2
2
2
C Bus Interface Unit allows the IXP45X/IXP46X network processors to serve as a
C bus allows the IXP45X/IXP46X network processors to interface to other I
C Bus Interface Unit is a peripheral device that resides on the IXP45X/IXP46X
C supports:
®
IXP46X Product Line of Network Processors
2
C bus.
®
processor, a full source or sink capable IEEE-1588
2
C Bus Specification for complete details on I
Intel
®
IXP45X and Intel
2
C bus. The I
®
IXP46X Product Line of Network Processors
2
C bus is a two-pin serial bus.
2
C bus via a
2
C bus
Datasheet
2
C
29