gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 66

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 16.
August 2006
66
EX_CLK
EX_ALE
EX_ADDR[24:0]
EX_WR_N
EX_RD_N
Note:
†
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Table 1 on page
Expansion Bus Interface (Sheet 1 of 3)
Reset
Power
on
H
H
H
H
Z
†
13.
Reset
VI
H
H
H
H
†
Software
Enables
Normal
Table 8 on page
Reset
After
Until
VO
VB
VB
VB
VI
Software
Configur
Possible
Enables
ations
VO / Z
After
VB
VB
VB
VI
43.
®
IXP45X and Intel
Type
TRI
I/O
I/O
I/O
I
†
Input clock signal used to sample all expansion interface inputs and clock all expansion interface
outputs.
Expansion bus Address-latch enable used for multiplexed address/data bus accesses, as an Advance
pin for Intel synchronous modes of operation/ZBT SRAM mode of operation, and LD_N for ZBT
SRAM. EX_ALE is always used by outbound transfers.
Expansion bus address used as an output for data accesses over the expansion bus when executing
outbound transactions and used as an input for data accesses over the expansion bus when
executing inbound transactions. Also, used as an input during reset to capture device configuration.
These signals have a weak pull-up resistor attached internally. Based on the desired configuration,
various address signals must be tied low in order for the device to operate in the desired mode. A
4.7 KΩ pull-down resistor is required to override these pull-up resistors. These pull-ups are disabled
when PLL_LOCK is asserted and the IXP45X/IXP46X network processors drive the signal based upon
grant. EX_ADDR is driven by IXP45X/IXP46X network processors except when grant is asserted to
an external master or during reset.
Very Important Note: See Intel
Developer’s Manual for additional details on address strapping.
Expansion bus write enable signal is used as an Intel-mode write strobe / Motorola-mode data
strobe (EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N) / ZBT SRAM mode read/
write_n(ZBT_RD_WR_N) for outbound transactions. This signal is an output for outbound
transactions.
Expansion bus write enable signal is used as a write enable signal to the IXP45X/IXP46X network
processors for inbound transaction support. This signal is an input for inbound transactions.
EX_WR_N is driven by IXP45X/IXP46X network processors unless grant is asserted to an external
master
Expansion bus read enable signal is used as an Intel-mode read strobe / Motorola-mode read-not-
write (EXPB_MOT_RNW) / TI mode read-not-write (TI_HR_W_N) / ZBT SRAM mode output enable
(ZBT_OE_N) for outbound transactions. This signal is an output for outbound transactions.
Expansion bus read enable signal is used as a read enable signal to the IXP45X/IXP46X network
processors for inbound transaction support. This signal is an input for inbound transactions.
EX_RD_N is driven by IXP45X/IXP46X network processors unless grant is asserted to an external
master.
®
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
Intel
®
IXP45X and Intel
®
IXP45X and Intel
Description
®
IXP46X Product Line of Network Processors Datasheet
®
IXP46X Product Line of Network Processors
Document Number:
306261-004US