gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 59

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 14.
Table 15.
August 2006
59
UTP_IP_ADDR[4:0]
UTP_IP_FCO
Note:
†
††
ETHB_TXCLK /
SMII_CLK
Note:
†
††
Name
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
For information on selecting the desired interface, see the Intel
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Please refer to Intel
Table 1 on page
Table 1 on page
UTOPIA Level 2/MII_A/ SMII Interface (Sheet 7 of 7)
MII/SMII Interfaces (Sheet 1 of 7)
Reset
Power
Power
Reset
on
Z
Z
on
®
Z
13.
13.
IXP45X and Intel
†
†
Reset
Reset
Z
Z
VI
†
†
Table 8 on page
Table 8 on page
Software
Software
Enables
®
Normal
Enables
Normal
Reset
After
Until
Reset
After
Until
IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired
Z
Z
VI
Software
Configur
Possible
Software
Enables
Possible
Configur
Enables
ations
ations
After
43.
43.
After
VO
VO
®
®
VI
IXP45X and Intel
IXP45X and Intel
®
Type
Type
I/O
TRI
IXP45X and Intel
I
†
†
Receive PHY address bus.
Used by the processor when operating in MPHY mode to poll and select a single PHY at any one
given time.
UTOPIA Input Data Flow Control Output signal: Also known as the RX_ENB_N.
In SPHY configurations, UTP_IP_FCO is used to inform the PHY that the processor is ready to
accept data.
In MPHY configurations, UTP_IP_FCO is used to select which PHY will drive the UTP_RX_DATA and
UTP_RX_SOC signals. The PHY is selected by placing the PHY’s address on the UTP_IP_ADDR and
bringing UTP_OP_FCO to logic 1 during the current clock, followed by the UTP_OP_FCO going to a
logic 0 on the next clock cycle.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
MII Mode of Operation:
Externally supplied transmit clock.
This MAC interface does not contain hardware hashing capabilities local to the interface.
SMII Mode of Operation:
125-MHz input clock used as the reference clock when operating in SMII or Source Synchronous
SMII mode of operation.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
®
®
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps operation
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
®
IXP46X Product Line of Network Processors Developer’s Manual.
Intel
®
IXP45X and Intel
®
Description
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-004US