gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 138

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gwixp465bad

Manufacturer Part Number
gwixp465bad
Description
Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
Manufacturer
ETC-unknow
Datasheet
5.6.2.7.3
Figure 42.
Intel
Datasheet
138
®
IXP45X and Intel
Note:
Processors Developer’s Manual, in the Expansion Bus Controller chapter’s “Using I/O
Wait” section.
I/O Wait Normal Phase Timing
Using I/O Wait
The EX_IOWAIT_N signal is available to be shared by devices attached to chip selects 0
through 7, when configured in Intel or Motorola modes of operation. The main purpose
of this signal is to properly communicate with slower devices requiring more time to
respond during data access. During idle cycles, the board is responsible for ensuring
that EX_IOWAIT_N is pulled-up. The Expansion bus controller will always ignore
EX_IOWAIT_N for synchronous Intel mode writes.
For details, see the Intel
EX_ADDR[23:0]
EX_DATA[15:0]
EX_ IOWAIT_N
EX_CS_ N[0]
Notice that the access is an Intel-style simplex read access. The data strobe phase is set to a value to last
three clock cycles. The data is returned from the peripheral device prior to the three clocks and the
peripheral device de-asserts EX_IOWAIT_N. The data strobe phase terminates after two clocks even though
the strobe phase was configured to pulse for three clocks.
EX_RD_N
®
EX_ CLK
IXP46X Product Line of Network Processors
Intel
®
IXP45X and Intel
T1=0 h
1 Cycle
®
IXP45X and Intel
T2=0 h
1 Cycle
Valid Address
®
IXP46X Product Line of Network Processors—Datasheet
T3=2h or 1h or 0h
®
Valid Data
3 Cycles
IXP46X Product Line of Network
2 Cycles
Document Number:
T4=0 h
1 Cycle
T5=0 h
1 Cycle
306261-004US
August 2006
B5242 -01

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