gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 24

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Table 4.
Intel
Datasheet
24
Notes:
1.
2.
DDRI SDRAM
Technology
®
128 Mbit
256 Mbit
512 Mbit
IXP45X and Intel
1 Gbit
Table indicates 32-bit-wide memory subsystem sizes
Table indicates 32-bit-wide memory page sizes
network processors. The 128/256/512-Mbit, 1-Gbit DDRI SDRAM devices comprise four
internal leaves. The MCU controls the leaf selects within 128/256/512-Mbit, 1-Gbit
DDRI SDRAM by toggling DDRI_BA[0] and DDRI_BA[1].
The two DDR SDRAM chip enables (DDRI_CS[1:0]#) support a DDRI SDRAM memory
subsystem consisting of two banks. The base address for the two contiguous banks are
programmed in the DDR SDRAM Base Register (SDBR) and must be aligned to a 32-
Mbyte boundary. The size of each DDR SDRAM bank is programmed with the DDR
SDRAM boundary registers (SBR0 and SBR1).
The memory controller is a 32-bit only interface. If a x16 memory chip is used, a
minimum of two memory chips would be required to facilitate the 32-bit interface
required by the IXP45X/IXP46X network processors. If ECC is required, additional
memories would need to be added. For more information on DDRI SDRAM support and
configuration see the Intel
The MCU supports two banks of DDR SDRAM. The MCU has support for unbuffered
DDRI 266 only.
Table 4
Supported DDRI Memory Configurations
Processors Developer’s Manual.
The memory controller internally interfaces to the North AHB, South AHB, and Memory
Port Interface with independent interfaces. This architecture allows DDRI SDRAM
transfers to be interleaved and pipelined to achieve maximum possible efficiency.
The maximum burst size supported to the DDRI SDRAM interface is eight 32-bit words.
This burst size allows the best efficiency/fairness performance between peripheral
accesses from the North AHB, the South AHB, and the MPI.
Arrangement
DDRI SDRAM
®
16M x 16
32M x 16
128M x 8
64M x 16
16M x 8
8M x 16
32M x 8
64M x 8
IXP46X Product Line of Network Processors
illustrates the supported DDR SDRAM configurations for the IXP45X/IXP46X
Intel
# Banks
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
®
IXP45X and Intel
Address Size
®
Row
12
12
13
13
13
13
14
14
IXP45X and Intel
Col
10
10
11
10
11
10
9
9
®
IXP46X Product Line of Network Processors—Datasheet
DDRI_BA[1]
I_AD[26]
I_AD[25]
I_AD[27]
I_AD[26]
I_AD[28]
I_AD[27]
I_AD[29]
I_AD[28]
®
Leaf Select
IXP46X Product Line of Network
DDRI_BA[0]
I_AD[25]
I_AD[24]
I_AD[26]
I_AD[25]
I_AD[27]
I_AD[26]
I_AD[28]
I_AD[27]
Document Number:
128 Mbyte
128 Mbyte
256 Mbyte
128 Mbyte
256 Mbyte
512 Mbyte
128 Mbyte
256 Mbyte
512 Mbyte
256 Mbyte
512 Mbyte
64 Mbyte
32 Mbyte
64 Mbyte
64 Mbyte
Memory
1 Gbyte
Total
Size
1
306261-004US
August 2006
Page
Size
4K
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