gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 18

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

3.1
3.1.1
Table 3.
Intel
Datasheet
18
®
IXP45X and Intel
Product Line of Network Processors Developer’s Manual.
Unless otherwise specified, the functional descriptions apply to all of the IXP45X/
IXP46X network processors. For specific information on supported interfaces, refer to
Table 1 on page
Figure 2 on page
These NPEs are high-performance, hardware-multi-threaded processors with additional
local-hardware-assist functionality used to off load highly processor-intensive functions
such as MII (MAC), CRC checking/generation, AAL segmentation and re-assembly, AES,
AES-CCM, DES, 3DES, SHA, MD-5, etc.
All instruction code for the NPEs are stored locally and is accessed using a dedicated
instruction memory bus. Likewise, a separate dedicated data memory bus allows
accesses to local code store as well as DDR SDRAM via the AHB bus.
These NPEs support processing of the dedicated peripherals that can include:
Key Functional Units
The following sections briefly describe the functional units and their interaction in the
system. For more detailed information, refer to the Intel
Network Processor Engines (NPEs)
The network processor engines (NPEs) are dedicated-function processors containing
hardware coprocessors integrated into the IXP45X/IXP46X network processors. The
NPEs are used to off load processing function required by the Intel XScale
Table 3
IXP45X/IXP46X network processors. These configurations are determined by the
factory programmed fuse settings or by software that configures the part during boot-
up (see the Expansion Bus Configuration Register 1 (EXP_CNFG1) in the Expansion Bus
Chapter of the Intel
Developer’s Manual for more details). The table assumes that all features are
supported on the processor. For details on feature support listed by processor, see
Table 1 on page
Network Processor Functions
Configuration 0
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7
• One UTOPIA Level 2 (Universal Test and Operation PHY Interface for ATM) interface
• Two High-Speed Serial (HSS) interfaces
• Up to three Media-Independent Interface (MII), up to three Serial Media
Independent Interfaces (SMII), or some combination of each.
®
Device
IXP46X Product Line of Network Processors
specifies the possible combination of interfaces for the NPEs contained on the
Intel
13. For model-specific block diagrams, see
13.
16, and
UTOPIA
®
®
X
X
X
IXP45X and Intel
IXP45X and Intel
Figure 3 on page
HSS
X
X
X
X
X
X
X
X
SMII A
MII /
SMII
SMII
MII
MII
MII
®
IXP46X Product Line of Network Processors—Datasheet
®
IXP46X Product Line of Network Processors
SMII B
MII /
17.
SMII
SMII
SMII
SMII
SMII
SMII
MII
MII
SMII C
MII /
SMII
SMII
SMII
MII
MII
MII
MII
MII
®
IXP45X and Intel
Document Number:
Figure 1 on page
AES /
DES /
3DES
X
X
X
X
X
X
X
X
HDLC
8
8
8
8
8
8
8
8
®
306261-004US
®
processor.
SHA, MD-
August 2006
15,
IXP46X
5
X
X
X
X
X
X
X
X