gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 127

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Datasheet—Intel
Table 66.
Figure 34.
August 2006
Document Number:
Intel Multiplexed Mode Values
Talepulse
Tale2addrhold
Tdval2valwrt
Twrpulse
Tdholdafterwr
Tale2valcs
Trdsetup
Trdhold
Trecov
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Intel Simplex Mode
®
306261-004US
IXP45X and Intel
Symbol
EX_ADDR
EX_CS_N
EX_WR_N
EX_RD_N
EX_DATA
EX_DATA
EX_CLK
The EX_ALE signal is extended form T to 4T nnsec based on the programming of the T1 timing
parameter. The parameter Tale2addrhold is fixed at T.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
T is the period of the clock measured in ns.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing was designed for a system load between 5pF and 60pF for high drive setting
Pulse width of ALE (ADDR is valid at the rising edge of ALE)
Valid address hold time after from falling edge of ALE
Write data valid prior to WR_N falling edge
Pulse width of the WR_N
Valid data after the rising edge of WR_N
Valid chip select after the falling edge of ALE
Data valid required before the rising edge of RD_N
Data hold required after the rising edge of RD_N
Time needed between successive accesses on expansion
interface.
®
IXP46X Product Line of Network Processors
T addr2valcs
1-4 Cycles
T1
Parameter
Intel
®
T dval2valwrt
IXP45X and Intel
1-4 Cycles
T2
Valid Address
1-16 Cycles
Output Data
T wrpulse
T rdsetup
T3
Input Data
®
IXP46X Product Line of Network Processors
T dhold2afterwr
1-4 Cycles
T4
T rdhold
Min.
14.7
1
1
1
1
1
1
2
1
1-16 Cycles
T recov
Max.
T5
16
16
4
1
4
4
4
Cycles 1,
Cycles 1, 2,
Cycles 3,
Cycles 4,
Cycles 5,
Cycles
Cycles
Units
ns
ns
A9586-01
Datasheet
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6
Notes
7
7
7
7
127
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