gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 137

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Datasheet—Intel
Table 76.
Figure 41.
August 2006
Document Number:
HPI-16 Non-Multiplexed Write Accesses Values
HPI*-16 Non-Multiplexed Write Mode
®
EX_ADDR[23:0]
Notes:
1.
2.
3.
4.
5.
6.
7.
306261-004US
IXP45X and Intel
T
T
T
T
T
Symbol
cs2hds1val
hds1_pulse
data_setup
add_setup
data_hold
EX_RDY_N
T
EX_WR_N
EX_RD_N
EX_DATA
recov
EX_CS_N
(hds1_n)
(hr_w_n)
EX_CLK
(hcs_n)
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
IXP45X/IXP46X network processors have had sufficient time to recognize the HRDY and hold the
address phase for at least one clock pulse after the HRDY is de-active.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the IXP45X/
IXP46X network processors have had sufficient time to recognize the HRDY and hold the data setup
phase for at least one clock pulse after the HRDY is de-active
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active
One cycle is the period of the Expansion Bus clock.
Timing was designed for a system load between 5 pF and 60 pF for high drive setting
(hrdy)
(hdin)
Tcs2hds1val
(ha)
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data
strobe being active.
Pulse width of the HDS1 data strobe
Data valid prior to the rising edge of the HDS1 data strobe.
Data valid after the rising edge of the HDS1 data strobe.
Time required between successive accesses on the
expansion interface.
®
IXP46X Product Line of Network Processors
T1
Tdata_setup
Thds1_pulse
T2
Tadd_setup
Parameter
Data
Intel
Valid
T3
®
Tdata_hold
IXP45X and Intel
T4
Trecov
®
T5
IXP46X Product Line of Network Processors
T1
Min.
11
3
4
4
4
2
T2
Max.
45
36
17
4
5
5
Valid
Data
T3
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Units
Datasheet
1, 5,
5,
2, 4,
3, 5,
3,
4,
T4
Notes
6
6
6
6
5
6
137