gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 23

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Datasheet—Intel
3.1.8
Note:
August 2006
Document Number:
DDRI SDRAM Controller
The IXP45X/IXP46X network processors integrate a high-performance, multi-ported
Memory Controller Unit (MCU) to provide a direct interface between the IXP45X/IXP46X
network processors and their local memory subsystem. The MCU supports:
The DDRI SDRAM interface provides a direct connection to a high-bandwidth and
reliable memory subsystem. The DDRI SDRAM interface is a 32-bit-wide data path.
An 8-bit Error Correction Code (ECC) across each 32-bit word improves system
reliability. It is important to note that ECC is also referred to as CB in many DIMM
specifications. The pins on IXP45X/IXP46X network processors are called
DDRI_CB[7:0]. ECC is only implemented in the 32-bit mode of operation. However, the
algorithm used to generate the 8-bit ECC is implemented over 64-bit.
The IXP455 network processor does not support ECC functionality.
The ECC circuitry is designed to operate always on a 64-bit word and when operating in
32-bit mode, the upper 32 bits are driven to zeros internally. To summarize the impact
to the customer, the full 8 bits of ECC must be stored and read from a memory array in
order for the ECC logic to work. An 8-bit-wide memory must be used when
implementing ECC.
The memory controller only corrects single bit ECC errors on read cycles. The ECC is
stored into the DDRI SDRAM array along with the data and is checked when the data is
read. If the code is incorrect, the MCU corrects the data (if possible) before reaching
the initiator of the read. ECC error scrubbing must be done with software. User-defined
fault correction software is responsible for scrubbing the memory array and handling
double-bit errors.
In order to limit double-bit errors from occurring, periodically reading the entire usable
memory array will allow the hardware unit within the memory controller to correct any
single-bit, ECC errors that may have occurred prior to these errors becoming double-bit
ECC errors. Using this method is system-dependent.
It is important to note as well, that when sub-word writes (byte writes or half-word
writes) to a 32-bit memory with ECC enabled, the memory controller will implement
read-modify writes. Implementing read-modify writes is important to understand when
understanding performance implications when writing software.
To understand a read-modify write, understanding that a byte to be written falls within
a 32-bit word which is addressed on a word-aligned boundary. When a byte write is
requested, the memory controller will read the 32-bit word which encompasses the
byte that is to be written. The memory controller will then modify the specified byte,
calculate a new ECC, and then write the entire 32-bit word back into the memory
location it was read from.
The value written back into the memory location will contain the 32-bit word with the
modified byte and the new ECC value.
®
• DDRI 266 SDRAM
• 128/256/512-Mbit, 1-Gbit DDRI SDRAM technology support
• Only unbuffered DRAM support (No registered DRAM support)
• Dedicated port for Intel XScale
• Between 32 Mbyte and 1 Gbyte of 32-bit DDR SDRAM for low-cost solutions
• Single-bit error correction, multi-bit detection support (ECC)
• 32-, 40-bit wide Memory Interfaces (non-ECC and ECC support)
306261-004US
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Intel
®
processor to DDR SDRAM
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Datasheet
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