gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 60

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 15.
August 2006
60
ETHB_TXDATA[3:0] /
SMII_TXDATA[0] /
SMII_TXDATA[1] /
SMII_TXDATA[2] /
SMII_TXDATA[3]
ETHB_TXEN /
SMII_TXCLK
ETHB_RXCLK /
SMII_RXCLK
Note:
†
††
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Please refer to Intel
Table 1 on page
MII/SMII Interfaces (Sheet 2 of 7)
Power
Reset
on
®
Z
Z
Z
13.
IXP45X and Intel
†
Reset
VI
0
0
†
Table 8 on page
Software
®
Enables
Normal
Reset
After
Until
IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired
VO
VO
VO
Software
Possible
Configur
Enables
ations
43.
After
®
VO
VO
VO
IXP45X and Intel
Type
O
O
I
†
MII Mode of Operation:
Transmit data bus to PHY, asserted synchronously with respect to ETHB_TXCLK. This MAC
interface does not contain hardware hashing capabilities local to the interface.
SMII Mode of Operation:
Each SMII_TXDATA line is an interface to a separate physical port.
ETHB_TXDATA[3] is multiplexed with SMII_TXDATA[3],
ETHB_TXDATA[2] is multiplexed with SMII_TXDATA[2],
ETHB_TXDATA[1] is multiplexed with SMII_TXDATA[1],
ETHB_TXDATA[0] is multiplexed with SMII_TXDATA[0]
The data on these signal are transmitted synchronously with respect to the rising edge of
SMII_CLK when operating as an SMII interface and synchronously with respect to the rising edge
of SMII_TXCLK when operating as a Source Synchronous SMII interface
MII Mode of Operation:
Indicates that the PHY is being presented with nibbles on the MII interface. Asserted
synchronously, with respect to ETHB_TXCLK, at the first nibble of the preamble and remains
asserted until all the nibbles of a frame are presented. This MAC interface does not contain
hardware hashing capabilities local to the interface.
SMII Mode of Operation:
125-MHz clock that is used to send data to a physical interface when operating in a Source
Synchronous SMII mode of operation.
MII Mode of Operation:
Externally supplied receive clock.
This MAC interface does not contain hardware hashing capabilities local to the interface.
SMII Mode of Operation:
125-MHz clock that is used to sample data being received from a physical interface when
operating in a Source Synchronous SMII mode of operation.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
®
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps operation
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
Intel
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-004US