gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 143

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Datasheet—Intel
Table 79.
5.6.2.11
Figure 47.
August 2006
Document Number:
Notes:
1.
2.
3.
4.
5.
6.
Symbol
T1
T2
T3
T4
T5
T6
T7
T8
T9
High-Speed, Serial Timing Values
JTAG
Boundary-Scan General Timings
®
306261-004US
IXP45X and Intel
HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by the
IXP45X/IXP46X network processors. The signals are shown to be synchronous for illustrative purposes and
are not required to be synchronous.
Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external source as
inputs into the IXP45X/IXP46X network processors. Always applicable to HSS_RXDATA.
The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling edge of the
given reference clock. HSS_RXFRAME and HSS_RXDATA signals are synchronous to HSS_RXCLK and
HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK.
Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP45X/IXP46X
network processors to an external source. Always applicable to HSS_TXDATA.
The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP45X/IXP46X
network processors. The slowest clock speed that can be accepted or driven is 512 KHz. The maximum
clock speed that can be accepted or driven is 8.192 MHz. The clock duty cycle accepted will be 50/50 +
20%.
Timing was designed for a system load between 5 pF and 30 pF for high drive setting
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the rising edge of clock
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the rising edge of clock
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the falling edge of clock
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the falling edge of clock
Rising edge of clock to output delay for HSS_TXFRAME,
HSS_RXFRAME, and HSS_TXDATA
Falling edge of clock to output delay for HSS_TXFRAME,
HSS_RXFRAME, and HSS_TXDATA
Output Hold Delay after rising edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
Output Hold Delay after falling edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
HSS_TXCLK period and HSS_RXCLK period
JTG_TMS, JTG_TDI
®
IXP46X Product Line of Network Processors
JTG_TDO
JTG_TCK
Parameter
T
bsoh
Intel
®
IXP45X and Intel
T
T
bsod
bsel
T
bsis
T
bsih
T
®
bsch
1/8.192 MHz 1/512 KHz
IXP46X Product Line of Network Processors
Min.
5
0
5
0
0
0
Max.
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
B0416-01
Datasheet
1, 2,
1, 2,
1, 2,
1, 2,
1,
1, 3,
1, 3,
1, 3,
5
Notes
4
3
3
3
3
4
4
4
143