gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 45

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 10.
August 2006
45
DDRI_CK[2:0]
DDRI_CK_N[2:0]
DDRI_CS_N[1:0]
DDRI_RAS_N
DDRI_CAS_N
DDRI_WE_N
DDRI_DM[4:0]
DDRI_BA[1:0]
DDRI_MA[13:0]
DDRI_DQ[31:0]
DDRI_CB[7:0]
DDRI_DQS[4:0]
DDRI_CKE[1:0]
Note:
†
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Name
Table 1 on page
DDR SDRAM Interface (Sheet 1 of 2)
Reset
Power
13.
on
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
†
Reset
b’00
VB
VB
VB
Z
Z
Z
Z
Z
Z
Z
0
1
†
Table 8 on page
Software
Enables
Normal
Reset
After
Until
VO
VO
VO
VO
VO
VO
VO
VO
VO
VB
VO
VB
VB
Software
Configur
43.
Possible
Enables
®
ations
After
IXP45X and Intel
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VB
VB
VB
Type
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
†
®
DDR SDRAM Clock Out — Provide the positive differential clocks to the external SDRAM
memory subsystem.
DDR SDRAM Clock Out — Provide the negative differential clocks to the external SDRAM
memory subsystem.
Chip Select — Must be asserted for all transactions to the DDR SDRAM device. One per bank.
Row Address Strobe — Indicates that the current address on DDRI_MA[13:0] is the row.
Column Address Strobe — Indicates that the current address on DDRI_MA[13:0] is the
column.
Write Strobe — Defines whether or not the current operation by the DDR SDRAM is to be a
read or a write.
Data Bus Mask — Controls the DDR SDRAM data input buffers. Asserting DDRI_WE_N causes
the data on DDRI_DQ[31:0] and DDRI_CB[7:0] to be written into the DDR SDRAM devices.
DDRI_DM[4:0] controls this operation on a per byte basis. DDRI_DM[3:0] are intended to
correspond to each byte of a word of data. DDRI_DM[4] is intended to be utilized for the ECC
byte of data.
DDR SDRAM Bank Selects — Controls which of the internal DDR SDRAM banks to read or write.
DDRI_BA[1:0] are used for all technology types supported.
Address bits 13 through 0 — Indicates the row or column to access depending on the state of
DDRI_RAS_N and DDRI_CAS_N.
Data Bus — 32-bit wide data bus.
ECC Bus — Eight-bit error correction code which accompanies the data on DDRI_DQ[31:0].
When ECC is disabled and not being used in a system design, these signals are not required for
any connection.
Data Strobes Differential — Strobes that accompany the data to be read or written from the
DDR SDRAM devices. Data is sampled on the negative and positive edges of these strobes.
DDRI_DQS[3:0] are intended to correspond to each byte of a word of data. DDRI_DQS4] is
intended to be utilized for the ECC byte of data.
Clock enables — One clock after DDRI_CKE[1:0] is de-asserted, data is latched on DQ[31:0]
and DDRI_CB[7:0]. Burst counters within DDR SDRAM device are not incremented. De-
asserting this signal places the DDR SDRAM in self-refresh mode. For normal operation,
DDRI_CKE[1:0] must be asserted.
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
Intel
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-004US