gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 31

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Datasheet—Intel
3.1.21
3.2
August 2006
Document Number:
Queue Manager
The Queue Manager provides a means for maintaining coherency for data handling
between various processors cores contained on the IXP45X/IXP46X network processors
(NPE to NPE, NPE to Intel XScale
buffers in an embedded 8-Kbyte SRAM. The Queue Manager also implements the status
flags and pointers required for each queue.
The Queue Manager manages 64 independent queues. Each queue is configurable for
buffer and entry size. Additionally status flags are maintained for each queue.
The Queue Manager interfaces include an Advanced High-performance Bus (AHB)
interface to the NPEs and Intel XScale
Flag Bus interface, an event bus (to the NPE condition select logic), and two interrupts
to the Intel XScale
The AHB interface is used for configuration of the Queue Manager and provides access
to queues, queue status, and SRAM. Individual queue status for queues 0-31 is
communicated to the NPEs via the flag bus. Combined queue status for queues 32-63
are communicated to the NPEs via the event bus. The two interrupts, one for queues 0-
31 and one for queues 32-63, provide status interrupts to the Intel XScale
Intel XScale
The Intel XScale technology is compliant with the Intel
instruction-set architecture (ISA). The Intel XScale
designed with Intel, 0.18-micron production semiconductor process technology. This
process technology — with the compactness of the Intel
enables the Intel XScale
producing industry-leading mW/MIPS performance.
Intel XScale
®
• Seven/eight-stage super-pipeline promotes high-speed, efficient performance
• 128-entry branch target buffer keeps pipeline filled with statistically correct branch
• 32-entry instruction memory-management unit for logical-to-physical address
• 32-entry data-memory management unit for logical-to-physical address
• 32-Kbyte instruction cache can hold entire programs, preventing processor stalls
• 32-Kbyte data cache reduces processor stalls caused by multi-cycle memory
• 2-Kbyte mini-data cache for frequently changing data streams avoids “thrashing”
• Four-entry, fill-and-pend buffers to promote processor efficiency by allowing “hit-
• Eight-entry write buffer allows the processor to continue execution while data is
• Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD
• Performance monitoring unit (PMU) furnishing two 32-bit event counters and one
306261-004US
IXP45X and Intel
choices
translation, access permissions, and Instruction-Cache (I-cache) attributes
translation, access permissions, Data-Cache (D-Cache) attributes
caused by multi-cycle memory accesses
accesses
of the D-cache
under-miss” operation with data caches
written to memory
multiplies with 40-bit accumulation for efficient, high-quality media and signal
processing
32-bit cycle counter for analysis of hit rates, etc.
®
processor features include:
®
®
IXP46X Product Line of Network Processors
®
processor.
Processor
®
processor to operate over a wide speed and power range,
®
Intel
processor, etc.). It maintains the queues as circular
®
®
IXP45X and Intel
processor (or any other AHB bus master), a
®
®
processor, shown in
IXP46X Product Line of Network Processors
®
®
StrongARM
StrongARM
*
*
Version 5TE
RISC ISA —
Figure
®
processor.
Datasheet
4, is
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