gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 62

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 15.
August 2006
62
ETHB_COL
ETHB_CRS/
SMII_SYNC/
SMII_TXSYNC
Note:
†
††
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Please refer to Intel
Table 1 on page
MII/SMII Interfaces (Sheet 4 of 7)
Power
Reset
on
®
Z
Z
13.
IXP45X and Intel
†
Reset
VI
Z
†
Table 8 on page
Software
®
Enables
Normal
Reset
After
Until
IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired
VI
Z
Software
Possible
Configur
Enables
VI / VO
ations
43.
After
®
VI
IXP45X and Intel
Type
I/O
I
†
MII Mode of Operation:
Asserted by the PHY when a collision is detected by the PHY. This MAC interface does not contain
hardware hashing capabilities local to the interface.
SMII Mode of Operation:
Not used.
When this interface is disabled via the NPE-B Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse
(refer to Expansion Bus Controller chapter of the Intel
of Network Processors Developer’s Manual) and is not being used in a system design, this
interface/signal is not required for any connection.
MII Mode of Operation:
Asserted by the PHY when the transmit medium or receive medium is active. De-asserted when
both the transmit and receive medium are idle. Remains asserted throughout the duration of a
collision condition. PHY asserts CRS asynchronously and de-asserts synchronously, with respect
to ETHB_RXCLK. This MAC interface does not contain hardware hashing capabilities local to the
interface.
SMII Mode of Operation:
In SMII Mode of Operation, this signal is an output that creates a synchronous pulse once every
10 SMII_CLK reference clocks to signal the start of the next 10 bits of data to be transmitted/
received. SMII_CLK Reference clock operates at 125MHz.
In Source Synchronous mode of operation, a synchronous pulse output created once every 10
SMII_TXCLK clocks to signal the start of the next 10 bits of data to be transmitted. SMII_TXCLK
operates at 125MHz.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the NPE-B
Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse (refer to Expansion Bus Controller chapter of
the Intel
and is not being used in a system design, this interface/signal is not required for any connection.
In MII mode of operation, this signal is a valid input. In SMII mode of operation this signal is a
valid output.
®
• When NPE B is configured in MII mode of operation and the signal is not being used, it
• When NPE B is configured in SMII mode of operation, this signal must be pulled high with a
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
should be pulled low through a 10-KΩ resistor.
10-KΩ resistor.
®
IXP45X and Intel
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Developer’s Manual)
®
Description
IXP46X Product Line of Network Processors Datasheet
®
IXP45X and Intel
Document Number:
®
IXP46X Product Line
306261-004US