gwixp465bad ETC-unknow, gwixp465bad Datasheet - Page 63

• Manufacturer Part Number: gwixp465bad
• Description: Network Proc 1.3v/1.4v/2.5v/3.3v 400mhz 544-pin Bga
• Manufacturer: ETC-unknow

Package Information
Table 15.
August 2006
63
ETH_MDIO
ETH_MDC
ETHC_TXCLK
ETHC_TXDATA[3:1]
ETHC_TXDATA[0] /
SMII_TXDATA[5]
ETHC_TXEN
Note:
†
††
Name
This table discusses all features supported on the Intel
see
For a legend of the Type codes, see
Please refer to Intel
Table 1 on page
MII/SMII Interfaces (Sheet 5 of 7)
Power
Reset
on
®
Z
Z
Z
Z
Z
Z
13.
IXP45X and Intel
†
Reset
VI
Z
Z
0
0
0
†
Table 8 on page
Software
®
Enables
Normal
Reset
After
Until
IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired
VO
VO
VO
VI
VI
Z
Software
Possible
Configur
Enables
VI / VO
ations
43.
After
®
VB
VO
VO
VO
VI
IXP45X and Intel
Type
I/O
I/O
O
O
O
I
†
Management data output. Provides the write data to both PHY devices connected to each MII
interface. An external pull-up resistor of 1.5K ohm is required on ETH_MDIO to properly quantify
the external PHYs used in the system. For specific implementation, see the IEEE 802.3
specification.
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.
Management data clock. Management data interface clock is used to clock the MDIO signal as an
output and sample the MDIO as an input. The ETH_MDC is an input on power up and can be
configured to be an output through an Intel API as documented in the Intel
Programmer’s Guide.
Externally supplied transmit clock.
This MAC contains hardware hashing capabilities local to the interface.
This signal should be pulled high through a 10-KΩ resistor when being utilized in SMII mode of
operation.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
MII Mode of Operation:
Transmit data bus to PHY, asserted synchronously with respect to ETHC_TXCLK. This MAC
contains hardware hashing capabilities local to the interface.
SMII Mode of Operation:
Not used in SMII mode of operation.
MII Mode of Operation:
Transmit data bus to PHY, asserted synchronously with respect to ETHC_TXCLK. This MAC
contains hardware hashing capabilities local to the interface.
SMII Mode of Operation:
The data on this signal is transmitted synchronously with respect to the rising edge of SMII_CLK
when operating as an SMII interface and synchronously with respect to the rising edge of
SMII_TXCLK when operating as a Source Synchronous SMII interface
Indicates that the PHY is being presented with nibbles on the MII interface. Asserted
synchronously, with respect to ETHC_TXCLK, at the first nibble of the preamble, and remains
asserted until all the nibbles of a frame are presented. This MAC contains hardware hashing
capabilities local to the interface.
®
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps operation
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
Intel
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
®
IXP400 Software
306261-004US