STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 11

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM32W108CB, STM32W108HB
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6 MHz operation can only be used when radio operations are not required since the radio
requires an accurate 12 MHz clock.
The ARM® Cortex-M3 in the STM32W108 has also been enhanced to support two separate
memory protection levels. Basic protection is available without using the MPU, but the usual
operation uses the MPU. The networking stack software runs in privileged mode, which
allows full, unrestricted access to all areas of the chip, while application code runs in user
mode. In user mode, reading or writing to certain areas of memory and registers is restricted
to prevent common software bugs from interfering with network software operation. Errant
writes are captured and details are reported to the developer to assist in tracking down and
fixing issues.
The STM32W108 having an embedded ARM core, is therefore compatible with all ARM
tools and software.
Embedded Flash memory
Up to 128 Kbytes of embedded Flash memory is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Nested vectored interrupt controller (NVIC)
The STM32W108 embeds a nested vectored interrupt controller able to handle up to 43
maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16
priority levels.
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This hardware block provides flexible interrupt management features with minimal interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
Doc ID 16252 Rev 2
Description
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