STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 36

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

System modules
5.2.2
Note:
5.2.3
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The Power Management module allows a special emulated deep sleep state that retains
memory and core domain power while in deep sleep.
Reset recording
The STM32W108 records the last reset condition that generated a restart to the system.
The reset conditions recorded are:
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The
All bits are mutually exclusive except the OPT_BYTE_FAIL bit which preserves the original
reset event when set.
While CPU Lockup is marked as a reset condition in software, CPU Lockup is not
specifically a reset event. CPU Lockup is set to indicate that the CPU entered an
unrecoverable exception. Execution stops but a reset is not applied. This is so that a
debugger can interpret the cause of the error. We recommend that in a live application (i.e.
no debugger attached) the watchdog be enabled by default so that the STM32W108 can be
restarted.
Reset generation
The Reset Generation module responds to reset sources and generates the following reset
signals:
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Reset event source register (RESET_EVENT)
POWER_HV
POWER_LV
RSTB
W_DOG
SW_RST
WAKE_UP_DSLEEP
OPT_BYTE_FAIL
PORESET
SYSRESET
DAPRESET
PRESETHV
PRESETLV
Always-on domain power supply failure
Core or memory domain power supply failure
NRST pin asserted
Watchdog timer expired
Software reset by SYSERSETREQ from ARM® Cortex-M3
CPU
Wake-up from deep sleep
Error check failed when reading option bytes from Flash
memory
Reset of the ARM® Cortex-M3 CPU and ARM® Cortex-M3
System Debug components (Flash Patch and Breakpoint,
Data Watchpoint and Trace, Instrumentation Trace Macrocell,
Nested Vectored Interrupt Controller). ARM defines
PORESET as the region that is reset when power is applied.
Reset of the ARM® Cortex-M3 CPU without resetting the
Core Debug and System Debug components, so that a live
system can be reset without disturbing the debug
configuration.
Reset to the SWJ's AHB Access Port (AHB-AP).
Peripheral reset for always-on power domain, for peripherals
that are required to retain their configuration across a deep
sleep cycle.
Peripheral reset for core power domain, for peripherals that
are not required to retain their configuration across a deep
sleep cycle.
Doc ID 16252 Rev 2
is used to read back the last reset event.
STM32W108CB, STM32W108HB