STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 136

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Analog-to-digital converter
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the regulator is factory trimmed to within 40 mV of 1.80 V. Offset and gain correction using
VREF or VDD_PADSA reduces both ADC gain errors and reference errors but it is limited by
the absolute accuracy of the supply. Correction using VREF is recommended because
VREF is calibrated by the ST HAL software against the factory-trimmed VDD_PADSA. The
ADC calibrates as a single-ended measurement. Differential signals require correction of
both their inputs.
Table 19
enabled, respectively.
Equation notes
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Table 19
Table 19.
The equations in
calibration signal GND is outside the voltage range of the buffer.
equations used when the input buffer is selected.
Offset corrected
Offset and gain corrected
using VREF, normalized to
VREF
Offset and gain corrected
using VDD_PADSA,
normalized to VDD_PADSA
All N are 16-bit numbers.
N
N
0x0000 as the conversion result. Instead, ground yields a value closer to 1/4 of the
maximum negative 2’s complement — for example, 0xC000 (-16384).
N
the maximum positive 2’s complement 0x7FFF (32767) as the conversion result.
Instead, VREF yields a value close to 1/4 of the maximum positive 2’s complement
when the input buffer is not selected (for example, 0x4000 (16384)) and yields a value
close to 1/4 of the maximum negative 2’s complement when the input buffer is selected
(for example, 0xC000 (-16384)).
N
value close to 0x0000 when the input buffer is not selected and yields a value closer to
3/8 of the maximum negative 2’s complement when the input buffer is selected (for
example, 0xA000 (-24576)).
N
<<16 indicates a bit shift left by 16 bits.
When calculating the voltage of VDD_PADSA (ADC_MUXn=11), V = (1/2) *
VDD_PADSA
Calculation Type
X
GND
VREF
VREF/2
VDD_PADSA
is a sampling of the desired analog source.
and
shows the equations used when the input buffer is disabled.
is a sampling of ground. Due to the ADC's internal design, ground does not yield
is a sampling of VREF. Due to the ADC's internal design, VREF does not yield
Offset and gain correction (ADC_HVSELn=0)
is a sampling of VREF/2. Due to of the ADC's internal design, VREF/2 yields a
Table 20
Table 19
is a sampling of the regulated supply, VDD_PADSA/2.
show the equations used when the input buffer is disabled and
cannot be applied when the input buffer is selected, as the
N
N
Doc ID 16252 Rev 2
=
=
2
N
Corrected Sample
×
(
(
N
=
N
(
(
N
X
N
(
X
N
VDD
VREF
−
−
X
N
V
_
−
GND
PADSA
GND
−
N
N
GND
)
)
GND
<<
<<
−
)
V
)
16
16
GND
STM32W108CB, STM32W108HB
)
V
=
Table 20
(
Absolute Voltage
N
V
×
=
VDD
(
N
shows the
×
2
VREF
2
16
14
_
PADSA
)
)