STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 42

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

System modules
5.4
5.4.1
5.4.2
5.4.3
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System timers
Watchdog timer
The STM32W108 integrates a watchdog timer which can be enabled to provide protection
against software crashes and ARM® Cortex-M3 CPU lockup. By default, it is disabled at
power up of the always-on power domain. The watchdog timer uses the calibrated 1 kHz
clock (CLK1K) as its reference and provides a nominal 2.048 s timeout. A low water mark
interrupt occurs at 1.792 s and triggers an NMI to the ARM® Cortex-M3 NVIC as an early
warning. When enabled, periodically reset the watchdog timer by writing to the
WDOG_RESTART register before it expires.
The watchdog timer can be paused when the debugger halts the ARM® Cortex-M3. To
enable this functionality, set the bit DBG_PAUSE in the SLEEP_CONFIG register.
If the low-frequency internal RC oscillator (OSCRC) is turned off during deep sleep, CLK1K
stops. As a consequence the watchdog timer stops counting and is effectively paused
during deep sleep.
The watchdog enable/disable bits are protected from accidental change by requiring a two
step process. To enable the watchdog timer the application must first write the enable code
0xEABE to the WDOG_CTRL register and then set the WDOG_EN register bit. To disable
the timer the application must write the disable code 0xDEAD to the WDOG_CTRL register
and then set the WDOG_DIS register bit.
Sleep timer
The STM32W108 integrates a 32-bit timer dedicated to system timing and waking from
sleep at specific times. The sleep timer can use either the calibrated 1 kHz
reference(CLK1K), or the 32 kHz crystal clock (CLK32K). The default clock source is the
internal 1 kHz clock. The sleep timer clock source is chosen with the SLEEPTMR_CLKSEL
register.
The sleep timer has a prescaler, a divider of the form 2^N, where N can be programmed
from 1 to 2^15. This divider allows for very long periods of sleep to be timed. The timer
provides two compare outputs and wrap detection, all of which can be used to generate an
interrupt or a wake up event.
The sleep timer is paused when the debugger halts the ARM® Cortex-M3. No additional
register bit must be set.
To save current during deep sleep, the low-frequency internal RC oscillator (OSCRC) can
be turned off. If OSCRC is turned off during deep sleep and a low-frequency 32.768 kHz
crystal oscillator is not being used, then the sleep timer will not operate during deep sleep
and sleep timer wake events cannot be used to wakeup the STM32W108.
Event timer
The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can
be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock.
FCLK is either the SCLK or PCLK as selected by CPU_CLK_SEL (see
switching on page
40).
Doc ID 16252 Rev 2
STM32W108CB, STM32W108HB
Section 5.3.5: Clock