STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 74

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Serial interfaces
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14
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[12:10] SC_RXSSEL: Status of the receive count saved in SCx_RXCNTSAVED (SPI slave
13
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[9] SC_RXFRMB: This bit is set when DMA receive buffer B reads a byte with a frame
[8] SC_RXFRMA: This bit is set when DMA receive buffer A reads a byte with a frame
[7] This bit is set when DMA receive buffer B reads a byte with a parity error from the
[6] This bit is set when DMA receive buffer A reads a byte with a parity error from the
[5] This bit is set when DMA receive buffer B was passed an overrun error from the
[4] This bit is set when DMA receive buffer A was passed an overrun error from the
[3] This bit is set when DMA transmit buffer B is active.
[2] This bit is set when DMA transmit buffer A is active.
[1] This bit is set when DMA receive buffer B is active.
[0] This bit is set when DMA receive buffer A is active.
mode) when nSSEL deasserts. Cleared when a receive buffer is loaded and when
the receive DMA is reset.
0: No count was saved because nSSEL did not deassert.
2: Buffer A's count was saved, nSSEL deasserted once.
3: Buffer B's count was saved, nSSEL deasserted once.
6: Buffer A's count was saved, nSSEL deasserted more than once.
7: Buffer B's count was saved, nSSEL deasserted more than once.
1, 4, 5: Reserved.
error from the receive FIFO. It is cleared the next time buffer B is loaded or when the
receive DMA is reset. (SC1 in UART mode only)
error from the receive FIFO. It is cleared the next time buffer A is loaded or when the
receive DMA is reset. (SC1 in UART mode only)
receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA
is reset. (SC1 in UART mode only)
receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA
is reset. (SC1 in UART mode only)
receive FIFO. Neither receive buffer was capable of accepting any more bytes
(unloaded), and the FIFO filled up. Buffer B was the next buffer to load, and when it
drained the FIFO the overrun error was passed up to the DMA and flagged with this
bit. Cleared the next time buffer B is loaded and when the receive DMA is reset.
receive FIFO. Neither receive buffer was capable of accepting any more bytes
(unloaded), and the FIFO filled up. Buffer A was the next buffer to load, and when it
drained the FIFO the overrun error was passed up to the DMA and flagged with this
bit. Cleared the next time buffer A is loaded and when the receive DMA is reset.
12
r
SC_RXSSEL
11
r
10
r
SC_RX
FRMB
9
r
Doc ID 16252 Rev 2
SC_RX
FRMA
8
r
SC_RX
PARB
7
r
SC_RX
PARA
6
r
SC_RX
OVFB
5
r
STM32W108CB, STM32W108HB
SC_R
XOVF
A
4
r
SC_TX
ACTB
3
r
SC_TX
ACTA
2
r
SC_RX
ACTB
1
r
SC_RX
ACTA
0
r