STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 118

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

General-purpose timers
8.3.5
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TIM_IC2F
[14:12] TIM_OC2M: Output Compare 2 Mode. (Applies only if TIM_CC2S = 0
TIM_OC2M
Timer x capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0xE018 (TIM1) and 0xF018 (TIM2)
Reset value:
Timer channels can be programmed as inputs (capture mode) or outputs (compare mode).
The direction of channel y is defined by TIM_CCyS in this register.
The other bits in this register have different functions in input and in output modes. The
TIM_OC* fields only apply to a channel configured as an output (TIM_CCyS = 0), and the
TIM_IC* fields only apply to a channel configured as an input (TIM_CCyS > 0).
[11] TIM_OC2BE: Output Compare 2 Buffer Enable. (Applies only if TIM_CC2S = 0
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Define the behavior of the output reference signal OC2REF from which OC2 derives. OC2REF
is active high whereas OC2''s active level depends on the TIM_CC2P bit.
000: Frozen - The comparison between the output compare register TIMx_CCR2 and the
counter TIMx_CNT has no effect on the outputs.
001: Set OC2REF to active on match. The OC2REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2)
010: Set OC2REF to inactive on match. OC2REF signal is forced low when the counter
TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2).
011: Toggle - OC2REF toggles when TIMx_CNT = TIMx_CCR2.
100: Force OC2REF inactive.
101: Force OC2REF active.
110: PWM mode 1 - In up-counting, OC2REF is active as long as TIMx_CNT < TIMx_CCR2,
otherwise OC2REF is inactive. In down-counting, OC2REF is inactive if
TIMx_CNT > TIMx_CCR2, otherwise OC2REF is active.
111: PWM mode 2 - In up-counting, OC2REF is inactive if TIMx_CNT < TIMx_CCR2, otherwise
OC2REF is active. In down-counting, OC2REF is active if TIMx_CNT > TIMx_CCR2, otherwise
it is inactive.
Note: In PWM mode 1 or 2, the OC2REF level changes only when the result of the
0: Buffer register for TIMx_CCR2 is disabled. TIMx_CCR2 can be written at anytime, the new
value is used by the shadow register immediately.
1: Buffer register for TIMx_CCR2 is enabled. Read/write operations access the buffer register.
TIMx_CCR2 buffer value is loaded in the shadow register at each update event.
Note: The PWM mode can be used without enabling the buffer register only in one pulse mode
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comparison changes or when the output compare mode switches from “frozen” mode to
“PWM” mode.
(TIM_OPM bit set in the TIMx_CR2 register), otherwise the behavior is undefined.
TIM_O
C2BE
TIM_IC2PSC
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0x0000 0000
TIM_O
C2FE
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TIM_CC2S
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Doc ID 16252 Rev 2
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8
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TIM_IC1F
TIM_OC1M
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5
STM32W108CB, STM32W108HB
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4
TIM_O
C1BE
TIM_IC1PSC
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3
TIM_O
C1FE
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2
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TIM_CC1S
1
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0