STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 125

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM32W108CB, STM32W108HB
8.3.10
8.3.11
31
rw
15
rw
31
rw
15
rw
30
rw
14
rw
30
rw
14
rw
[15:0] TIM_ARR: Auto-reload value
[15:0] TIM_CCR: Capture/compare value
Timer x auto-reload register (TIMx_ARR)
Address offset: 0xE02C (TIM1) and 0xF02C (TIM2)
Reset value:
Timer x capture/compare 1 register (TIMx_CCR1)
Address offset: 0xE034 (TIM1) and 0xF034 (TIM2)
Reset value:
29
rw
13
rw
29
rw
13
rw
TIM_ARR is the value to be loaded in the shadow auto-reload register.
The auto-reload register is buffered. Writing or reading the auto-reload register accesses the
buffer register. The content of the buffer register is transfered in the shadow register
permanently or at each update event UEV, depending on the auto-reload buffer enable bit
(TIM_ARBE) in TMRx_CR1 register. The update event is sent when the counter reaches the
overflow point (or underflow point when down-counting) and if the TIM_UDIS bit equals 0 in the
TMRx_CR1 register. It can also be generated by software. The counter is blocked while the
auto-reload value is 0.
If the CC1 channel is configured as an output (TIM_CC1S = 0):
TIM_CCR1 is the buffer value to be loaded in the actual capture/compare 1 register. It is loaded
permanently if the preload feature is not selected in the TMR1_CCMR1 register (bit OC1PE).
Otherwise the buffer value is copied to the shadow capture/compare 1 register when an update
event occurs. The active capture/compare register contains the value to be compared to the
counter TMR1_CNT and signaled on the OC1 output.
If the CC1 channel is configured as an input (TIM_CC1S is not 0):
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
28
12
28
12
rw
rw
rw
rw
27
11
27
11
rw
rw
rw
rw
0x0000 0000
0x0000 0000
26
10
26
10
rw
rw
rw
rw
25
25
rw
rw
rw
rw
9
9
Doc ID 16252 Rev 2
24
24
rw
rw
rw
rw
8
8
TIM_CCR
TIM_ARR
23
rw
rw
23
rw
rw
7
7
22
22
rw
rw
rw
rw
6
6
21
rw
rw
21
rw
rw
5
5
20
rw
rw
20
rw
rw
4
4
General-purpose timers
19
rw
rw
19
rw
rw
3
3
18
18
rw
rw
rw
rw
2
2
17
17
rw
rw
rw
rw
1
1
125/179
16
rw
rw
16
rw
rw
0
0