STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 114

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

General-purpose timers
8.3.3
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TIM_E
TP
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15
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TIM_E
CE
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14
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Timer x slave mode control register (TIMx_SMCR)
Address offset: 0xE008 (TIM1) and 0xF008 (TIM2)
Reset value:
[6:4] TIM_MMS: Master Mode Selection
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13
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TIM_ETPS
This selects the information to be sent in master mode to a slave timer for synchronization
using the trigger output (TRGO).
000: Reset - the TIM_UG bit in the TMRx_EGR register is trigger output.
If the reset is generated by the trigger input (slave mode controller configured in reset mode),
then the signal on TRGO is delayed compared to the actual reset.
001: Enable - counter enable signal CNT_EN is trigger output.
This mode is used to start both timers at the same time or to control a window in which a slave
timer is enabled. The counter enable signal is generated by either the TIM_CEN control bit or
the trigger input when configured in gated mode. When the counter enable signal is controlled
by the trigger input there is a delay on TRGO except if the master/slave mode is selected (see
the TIM_MSM bit description in TMRx_SMCR register).
010: Update - update event is trigger output.
This mode allows a master timer to be a prescaler for a slave timer.
011: Compare Pulse.
The trigger output sends a positive pulse when the TIM_CC1IF flag is to be set (even if it was
already high) as soon as a capture or a compare match occurs.
100: Compare - OC1REF signal is trigger output.
101: Compare - OC2REF signal is trigger output.
110: Compare - OC3REF signal is trigger output.
111: Compare - OC4REF signal is trigger output.
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12
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27
11
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0x0000 0000
26
10
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TIM_ETF
25
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9
Doc ID 16252 Rev 2
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8
TIM_M
SM
23
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7
22
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6
TIM_TS
21
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5
STM32W108CB, STM32W108HB
20
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4
19
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3
18
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2
TIM_SMS
17
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1
16
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0