STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 52

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

General-purpose input/outputs
6.3
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External interrupts have individual triggering and filtering options selected using the
registers GPIO_INTCFGA, GPIO_INTCFGB, GPIO_INTCFGC, and GPIO_INTCFGD. The
bit field GPIO_INTMOD of the GPIO_INTCFGx register enables IRQx's second level
interrupt and selects the triggering mode: 0 is disabled; 1 for rising edge; 2 for falling edge; 3
for both edges; 4 for active high level; 5 for active low level. The minimum width needed to
latch an unfiltered external interrupt in both level- and edge-triggered mode is 80 ns. With
the digital filter enabled (the GPIO_INTFILT bit in the GPIO_INTCFGx register is set), the
minimum width needed is 450 ns.
The register INT_GPIOFLAG is the second-level interrupt flag register that indicates
pending external interrupts. Writing 1 to a bit in the INT_GPIOFLAG register clears the flag
while writing 0 has no effect. If the interrupt is level-triggered, the flag bit is set again
immediately after being cleared if its input is still in the active state.
Two of the four external interrupts, IRQA and IRQB, have fixed pin assignments. The other
two external interrupts, IRQC and IRQD, can use any GPIO pin. The GPIO_IRQCSEL and
GPIO_IRQDSEL registers specify the GPIO pins assigned to IRQC and IRQD, respectively.
Table 7
GPIO pin used for the external interrupt.
Table 7.
In some cases, it may be useful to assign IRQC or IRQD to an input also in use by a
peripheral, for example to generate an interrupt from the slave select signal (nSSEL) in an
SPI slave mode interface.
Refer to
STM32W108 interrupt system.
Debug control and status
Two GPIO registers are largely concerned with debugger functions. GPIO_DBGCFG can
disable debugger operation, but has other miscellaneous control bits as well.
GPIO_DBGSTAT, a read-only register, returns status related to debugger activity
(GPIO_FORCEDBG and GPIO_SWEN), as well a flag (GPIO_BOOTMODE) indicating
whether nBOOTMODE was asserted at the last power-on or NRST-based reset.
GPIO_IRQxSEL
shows how the GPIO_IRQCSEL and GPIO_IRQDSEL register values select the
0
1
2
3
4
5
6
7
Section 10: Interrupts on page 143
IRQC/D GPIO selection
GPIO
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
GPIO_IRQxSEL
Doc ID 16252 Rev 2
10
11
12
13
14
15
8
9
for further information regarding the
GPIO
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
STM32W108CB, STM32W108HB
GPIO_IRQxSEL
16
17
18
19
20
21
22
23
GPIO
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7