STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 47

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM32W108CB, STM32W108HB
Note:
6.1.2
Because GPIO port registers' functions are identical, the notation Px is used here to refer to
PA, PB, or PC. For example, GPIO_PxIN refers to the registers GPIO_PAIN, GPIO_PBIN,
and GPIO_PCIN.
Each of the three GPIO ports has the following registers whose low-order eight bits
correspond to the port's eight GPIO pins:
●
●
●
●
●
In addition to these registers, each port has a pair of configuration registers,
GPIO_PxCFGH and GPIO_PxCFGL. These registers specify the basic operating mode for
the port's pins. GPIO_PxCFGL configures the pins Px[3:0] and GPIO_PxCFGH configures
the pins Px[7:4]. For brevity, the notation GPIO_PxCFGH/L refers to the pair of configuration
registers.
Five GPIO pins (PA6, PA7, PB6, PB7 and PC0) can sink and source higher current than
standard GPIO outputs. Refer to
information.
Configuration
Each pin has a 4-bit configuration value in the GPIO_PxCFGH/L register. The various GPIO
modes and their 4 bit configuration values are shown in
Table 4.
If a GPIO has two peripherals that can be the source of alternate output mode data, then
other registers in addition to GPIO_PxCFGH/L determine which peripheral controls the
output.
Analog
Input (floating)
Input (pull-up or pull-
down)
Output (push-pull)
Output (open-drain)
Alternate Output (push-
pull)
Alternate Output (open-
drain)
Alternate Output (push-
pull) SPI SCLK Mode
GPIO_PxIN (input data register) returns the pin level (unless in analog mode).
GPIO_PxOUT (output data register) controls the output level in normal output mode.
GPIO_PxCLR (clear output data register) clears bits in GPIO_PxOUT.
GPIO_PxSET (set output data register) sets bits in GPIO_PxOUT.
GPIO_PxWAKE (wake monitor register) specifies the pins that can wake the
STM32W108.
GPIO Mode
GPIO configuration modes
0x0
0x4
0x8
0x1
0x5
0x9
0xD
0xB
GPIO_PxCFGH/L
Doc ID 16252 Rev 2
Table 41: Digital I/O specifications on page 169
Analog input or output. When in analog mode, the
digital input (GPIO_PxIN) always reads 1.
Digital input without an internal pull up or pull down.
Output is disabled.
Digital input with an internal pull up or pull down. A set
bit in GPIO_PxOUT selects pull up and a cleared bit
selects pull down. Output is disabled.
Push-pull output. GPIO_PxOUT controls the output.
Open-drain output. GPIO_PxOUT controls the output.
If a pull up is required, it must be external.
Push-pull output. An onboard peripheral controls the
output.
Open-drain output. An onboard peripheral controls the
output. If a pull up is required, it must be external.
Push-pull output mode only for SPI master mode
SCLK pins.
Table
General-purpose input/outputs
Description
4.
for more
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